Unified Coverage Report :: Module :: pwrmgr

Module : pwrmgr

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.62	100.00	83.87	99.21		100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_pwrmgr_component_0.1/rtl/pwrmgr.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	96.62	100.00	83.87	99.21		100.00	100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.62	100.00	83.87	99.21		100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.75	98.23	96.43	99.44	96.00	96.37	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
clkmgr_pwrmgr_sva_if	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
i_wake_info	100.00	100.00	100.00			100.00
intr_wakeup	93.75	100.00	75.00			100.00	100.00
pwrmgr_clock_enables_sva_if	100.00	100.00	100.00				100.00
pwrmgr_csr_assert	100.00						100.00
pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00
pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_cdc	100.00	100.00	100.00			100.00	100.00
u_esc_clk_buf	100.00	100.00
u_esc_rst_buf	100.00	100.00
u_esc_rx	98.21			98.21
u_esc_timeout	92.79	100.00	75.00			96.15	100.00
u_esc_timeout_sync	100.00	100.00				100.00
u_fsm	98.66	100.00	98.44		94.87	100.00	100.00
u_ndm_sync	100.00	100.00				100.00
u_prim_lc_sync_dft_en	100.00	100.00				100.00	100.00
u_prim_lc_sync_hw_debug_en	100.00	100.00				100.00	100.00
u_reg	97.19	96.01	97.42	100.00		92.53	100.00
u_slow_fsm	99.41	100.00	97.06		100.00	100.00	100.00
u_sw_req_buf	100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
ALWAYS	178	4	4	100.00
ALWAYS	213	4	4	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	229	1	1	100.00
CONT_ASSIGN	230	1	1	100.00
CONT_ASSIGN	232	1	1	100.00
CONT_ASSIGN	233	1	1	100.00
CONT_ASSIGN	246	1	1	100.00
CONT_ASSIGN	334	1	1	100.00
ALWAYS	337	6	6	100.00
CONT_ASSIGN	346	1	1	100.00
CONT_ASSIGN	348	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	357	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	372	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	500	1	1	100.00
CONT_ASSIGN	504	1	1	100.00
CONT_ASSIGN	512	1	1	100.00
CONT_ASSIGN	512	1	1	100.00
CONT_ASSIGN	512	1	1	100.00
CONT_ASSIGN	512	1	1	100.00
CONT_ASSIGN	512	1	1	100.00
CONT_ASSIGN	512	1	1	100.00
CONT_ASSIGN	517	1	1	100.00
CONT_ASSIGN	517	1	1	100.00
CONT_ASSIGN	521	1	1	100.00
CONT_ASSIGN	578	1	1	100.00
CONT_ASSIGN	651	1	1	100.00
CONT_ASSIGN	655	1	1	100.00
CONT_ASSIGN	712	0	0
ALWAYS	716	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_pwrmgr_component_0.1/rtl/pwrmgr.sv' or '../src/lowrisc_ip_pwrmgr_component_0.1/rtl/pwrmgr.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
108	1	1
116	1	1
117	1	1
178	1	1
179	1	1
180	1	1
182	1	1
			MISSING_ELSE
213	1	1
214	1	1
215	1	1
217	1	1
			MISSING_ELSE
228	1	1
229	1	1
230	1	1
232	1	1
233	1	1
246	1	1
334	1	1
337	1	1
338	1	1
339	1	1
340	1	1
341	1	1
342	1	1
			MISSING_ELSE
346	1	1
348	1	1
350	1	1
357	1	1
358	1	1
372	1	1
377	1	1
475	1	1
500	1	1
504	1	1
512	6	6
517	2	2
521	1	1
578	1	1
651	1	1
655	1	1
712		unreachable
716		unreachable
717		unreachable
719		unreachable

---

Cond Coverage for Module : pwrmgr

	Total	Covered	Percent
Conditions	31	26	83.87
Logical	31	26	83.87
Non-Logical	0	0
Event	0	0

 LINE       232
 EXPRESSION (esc_rst_req_q | esc_timeout_lc_q)
             ------1------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T5,T14,T15

 LINE       339
 EXPRESSION (((!lowpwr_cfg_wen)) && (clr_cfg_lock || wkup))
             ---------1---------    -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       339
 SUB-EXPRESSION (clr_cfg_lock || wkup)
                 ------1-----    --2-

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T14,T16
1	0	Covered	T1,T2,T3

 LINE       358
 EXPRESSION (peri_reqs_masked.rstreqs[pwrmgr_reg_pkg::ResetMainPwrIdx] | reg2hw.fault_status.main_pd_glitch.q)
             ----------------------------1----------------------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T17,T18,T19
1	0	Covered	T5,T6,T10

 LINE       372
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       377
 EXPRESSION (reg2hw.fault_status.reg_intg_err.q | reg2hw.fault_status.esc_timeout.q | reg2hw.fault_status.main_pd_glitch.q)
             -----------------1----------------   ----------------2----------------   ------------------3-----------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T5,T6,T10
0	1	0	Covered	T11,T12,T13
1	0	0	Covered	T20,T21,T22

 LINE       401
 EXPRESSION (reg2hw.cfg_cdc_sync.qe & reg2hw.cfg_cdc_sync.q)
             -----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       578
 EXPRESSION (reg2hw.control.low_power_hint.q == LowPower)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       580
 EXPRESSION (core_sleeping & low_power_hint)
             ------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       651
 EXPRESSION (reg2hw.wake_info.abort.qe | reg2hw.wake_info.fall_through.qe | reg2hw.wake_info.reasons.qe)
             ------------1------------   ----------------2---------------   -------------3-------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

---

Toggle Coverage for Module : pwrmgr

	Total	Covered	Percent
Totals	81	79	97.53
Total Bits	508	504	99.21
Total Bits 0->1	254	252	99.21
Total Bits 1->0	254	252	99.21

Ports	81	79	97.53
Port Bits	508	504	99.21
Port Bits 0->1	254	252	99.21
Port Bits 1->0	254	252	99.21

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_slow_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_slow_ni	Yes	Yes	T2,T5,T6	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T5,T6	Yes	T1,T2,T3	INPUT
rst_main_ni	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	INPUT
clk_lc_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_lc_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_esc_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_esc_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T9,T14,T15	Yes	T9,T14,T15	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T14,T23,T24	Yes	T14,T23,T24	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
pwr_ast_i.main_pok	Yes	Yes	T1,T4,T6	Yes	T1,T2,T3	INPUT
pwr_ast_i.usb_clk_val	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
pwr_ast_i.io_clk_val	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
pwr_ast_i.core_clk_val	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
pwr_ast_i.slow_clk_val	No	No		No		INPUT
pwr_ast_o.usb_clk_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwr_ast_o.io_clk_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwr_ast_o.core_clk_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwr_ast_o.slow_clk_en	No	No		No		OUTPUT
pwr_ast_o.pwr_clamp	Yes	Yes	T1,T2,T3	Yes	T1,T2,T4	OUTPUT
pwr_ast_o.pwr_clamp_env	Yes	Yes	T1,T2,T3	Yes	T1,T2,T4	OUTPUT
pwr_ast_o.main_pd_n	Yes	Yes	T1,T4,T6	Yes	T1,T4,T6	OUTPUT
pwr_rst_i.rst_sys_src_n[1:0]	Yes	Yes	T2,T3,T5	Yes	T1,T2,T3	INPUT
pwr_rst_i.rst_lc_src_n[1:0]	Yes	Yes	T2,T3,T5	Yes	T1,T2,T3	INPUT
pwr_rst_o.reset_cause[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwr_rst_o.rstreqs[4:0]	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	OUTPUT
pwr_rst_o.rst_sys_req[1:0]	Yes	Yes	T1,T2,T3	Yes	T2,T3,T5	OUTPUT
pwr_rst_o.rst_lc_req[1:0]	Yes	Yes	T1,T2,T3	Yes	T2,T3,T5	OUTPUT
pwr_clk_o.usb_ip_clk_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwr_clk_o.io_ip_clk_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwr_clk_o.main_ip_clk_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwr_clk_i.usb_status	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
pwr_clk_i.io_status	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
pwr_clk_i.main_status	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
pwr_otp_i.otp_idle	Yes	Yes	T14,T16,T25	Yes	T1,T2,T3	INPUT
pwr_otp_i.otp_done	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
pwr_otp_o.otp_init	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwr_lc_i.lc_idle	Yes	Yes	T14,T16,T25	Yes	T1,T2,T3	INPUT
pwr_lc_i.lc_done	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
pwr_lc_o.lc_init	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwr_flash_i.flash_idle	Yes	Yes	T14,T16,T25	Yes	T1,T2,T3	INPUT
pwr_cpu_i.core_sleeping	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
fetch_en_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
lc_hw_debug_en_i[3:0]	Yes	Yes	T10,T26,T27	Yes	T10,T26,T27	INPUT
lc_dft_en_i[3:0]	Yes	Yes	T10,T26,T27	Yes	T10,T26,T27	INPUT
wakeups_i[5:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
rstreqs_i[1:0]	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	INPUT
ndmreset_req_i	Yes	Yes	T5,T14,T15	Yes	T5,T14,T15	INPUT
strap_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
low_power_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
rom_ctrl_i.good[3:0]	Yes	Yes	T6,T10,T14	Yes	T6,T10,T14	INPUT
rom_ctrl_i.done[3:0]	Yes	Yes	T6,T10,T14	Yes	T6,T10,T14	INPUT
sw_rst_req_i[3:0]	Yes	Yes	T5,T14,T15	Yes	T5,T14,T15	INPUT
esc_rst_tx_i.esc_n	Yes	Yes	T5,T14,T15	Yes	T5,T14,T15	INPUT
esc_rst_tx_i.esc_p	Yes	Yes	T5,T14,T15	Yes	T5,T14,T15	INPUT
esc_rst_rx_o.resp_n	Yes	Yes	T5,T14,T15	Yes	T5,T14,T15	OUTPUT
esc_rst_rx_o.resp_p	Yes	Yes	T5,T14,T15	Yes	T5,T14,T15	OUTPUT
intr_wakeup_o	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : pwrmgr

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
IF	178	3	3	100.00
IF	213	3	3	100.00
IF	337	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_pwrmgr_component_0.1/rtl/pwrmgr.sv' or '../src/lowrisc_ip_pwrmgr_component_0.1/rtl/pwrmgr.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	178	if ((!rst_lc_n))
-2-:	180	if (esc_rst_req_d)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T5,T14,T15
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	213	if ((!rst_lc_n))
-2-:	215	if (esc_timeout_lc_d)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	337	if ((!rst_ni))
-2-:	339	if (((!lowpwr_cfg_wen) && (clr_cfg_lock || wkup)))
-3-:	341	if (low_power_hint)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	18	18	100.00	18	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	18	18	100.00	18	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertNumCheck_A	926	926	0	0
AlertsKnownO_A	18447268	18060426	0	0
AstKnownO_A	18447268	18060426	0	0
ClkKnownO_A	18447268	18060426	0	0
ClkRatio_A	18447268	18060426	0	0
FpvSecCmFsmCheck_A	18447268	70	0	0
FpvSecCmRegWeOnehotCheck_A	18447268	70	0	0
FpvSecCmSlowFsmCheck_A	3532422	70	0	0
GlitchStatusPersist_A	18447268	4566	0	0
IntrKnownO_A	18447268	18060426	0	0
LcKnownO_A	18447268	18060426	0	0
OtpKnownO_A	18447268	18060426	0	0
PwrmgrSecCmEscToLCReset_A	18447268	1500	0	0
PwrmgrSecCmEscToSlowResetReq_A	3532422	10537	0	0
PwrmgrSecCmFsmEscToResetReq_A	18447268	70084	0	0
RstKnownO_A	18447268	18060426	0	0
TlAReadyKnownO_A	18447268	18060426	0	0
TlDValidKnownO_A	18447268	18060426	0	0

AlertNumCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

AlertsKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18447268	18060426	0	0
T1	5285	5195	0	0
T2	3347	2975	0	0
T3	2588	2531	0	0
T4	4257	4202	0	0
T5	2832	1863	0	0
T6	14165	14042	0	0
T7	10154	10069	0	0
T8	5489	5405	0	0
T9	1192	1131	0	0
T10	60197	60144	0	0

AstKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18447268	18060426	0	0
T1	5285	5195	0	0
T2	3347	2975	0	0
T3	2588	2531	0	0
T4	4257	4202	0	0
T5	2832	1863	0	0
T6	14165	14042	0	0
T7	10154	10069	0	0
T8	5489	5405	0	0
T9	1192	1131	0	0
T10	60197	60144	0	0

ClkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18447268	18060426	0	0
T1	5285	5195	0	0
T2	3347	2975	0	0
T3	2588	2531	0	0
T4	4257	4202	0	0
T5	2832	1863	0	0
T6	14165	14042	0	0
T7	10154	10069	0	0
T8	5489	5405	0	0
T9	1192	1131	0	0
T10	60197	60144	0	0

ClkRatio_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18447268	18060426	0	0
T1	5285	5195	0	0
T2	3347	2975	0	0
T3	2588	2531	0	0
T4	4257	4202	0	0
T5	2832	1863	0	0
T6	14165	14042	0	0
T7	10154	10069	0	0
T8	5489	5405	0	0
T9	1192	1131	0	0
T10	60197	60144	0	0

FpvSecCmFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18447268	70	0	0
T20	13235	10	0	0
T21	0	10	0	0
T22	0	10	0	0
T28	0	20	0	0
T29	0	20	0	0
T30	1166	0	0	0
T31	1579	0	0	0
T32	3067	0	0	0
T33	842	0	0	0
T34	22842	0	0	0
T35	1079	0	0	0
T36	21195	0	0	0
T37	5752	0	0	0
T38	1292	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18447268	70	0	0
T20	13235	10	0	0
T21	0	10	0	0
T22	0	10	0	0
T28	0	20	0	0
T29	0	20	0	0
T30	1166	0	0	0
T31	1579	0	0	0
T32	3067	0	0	0
T33	842	0	0	0
T34	22842	0	0	0
T35	1079	0	0	0
T36	21195	0	0	0
T37	5752	0	0	0
T38	1292	0	0	0

FpvSecCmSlowFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3532422	70	0	0
T20	2573	10	0	0
T21	0	10	0	0
T22	0	10	0	0
T28	0	20	0	0
T29	0	20	0	0
T30	234	0	0	0
T31	479	0	0	0
T32	292	0	0	0
T33	286	0	0	0
T34	8145	0	0	0
T35	336	0	0	0
T36	7536	0	0	0
T37	443	0	0	0
T38	443	0	0	0

GlitchStatusPersist_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18447268	4566	0	0
T5	2832	4	0	0
T6	14165	2	0	0
T7	10154	0	0	0
T8	5489	0	0	0
T9	1192	0	0	0
T10	60197	22	0	0
T14	395238	62	0	0
T15	0	3	0	0
T26	0	13	0	0
T27	0	1	0	0
T39	56262	9	0	0
T40	0	5	0	0
T41	0	14	0	0
T42	3619	0	0	0
T43	10590	0	0	0

IntrKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18447268	18060426	0	0
T1	5285	5195	0	0
T2	3347	2975	0	0
T3	2588	2531	0	0
T4	4257	4202	0	0
T5	2832	1863	0	0
T6	14165	14042	0	0
T7	10154	10069	0	0
T8	5489	5405	0	0
T9	1192	1131	0	0
T10	60197	60144	0	0

LcKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18447268	18060426	0	0
T1	5285	5195	0	0
T2	3347	2975	0	0
T3	2588	2531	0	0
T4	4257	4202	0	0
T5	2832	1863	0	0
T6	14165	14042	0	0
T7	10154	10069	0	0
T8	5489	5405	0	0
T9	1192	1131	0	0
T10	60197	60144	0	0

OtpKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18447268	18060426	0	0
T1	5285	5195	0	0
T2	3347	2975	0	0
T3	2588	2531	0	0
T4	4257	4202	0	0
T5	2832	1863	0	0
T6	14165	14042	0	0
T7	10154	10069	0	0
T8	5489	5405	0	0
T9	1192	1131	0	0
T10	60197	60144	0	0

PwrmgrSecCmEscToLCReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18447268	1500	0	0
T5	2832	2	0	0
T6	14165	0	0	0
T7	10154	0	0	0
T8	5489	0	0	0
T9	1192	0	0	0
T10	60197	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T14	395238	18	0	0
T15	0	4	0	0
T27	0	1	0	0
T39	56262	0	0	0
T40	0	2	0	0
T42	3619	0	0	0
T43	10590	0	0	0
T44	0	2	0	0
T45	0	2	0	0
T46	0	2	0	0

PwrmgrSecCmEscToSlowResetReq_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3532422	10537	0	0
T5	1510	23	0	0
T6	1604	0	0	0
T7	1571	0	0	0
T8	2019	0	0	0
T9	188	0	0	0
T10	6040	0	0	0
T14	38348	105	0	0
T15	0	15	0	0
T27	0	6	0	0
T39	6295	0	0	0
T40	0	42	0	0
T42	3763	0	0	0
T43	2144	0	0	0
T44	0	39	0	0
T45	0	18	0	0
T46	0	9	0	0
T47	0	6	0	0
T48	0	9	0	0

PwrmgrSecCmFsmEscToResetReq_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18447268	70084	0	0
T5	2832	46	0	0
T6	14165	0	0	0
T7	10154	0	0	0
T8	5489	0	0	0
T9	1192	0	0	0
T10	60197	0	0	0
T11	0	14	0	0
T14	395238	1328	0	0
T15	0	164	0	0
T27	0	57	0	0
T39	56262	0	0	0
T40	0	141	0	0
T42	3619	0	0	0
T43	10590	0	0	0
T44	0	79	0	0
T45	0	52	0	0
T47	0	11	0	0
T48	0	5	0	0

RstKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18447268	18060426	0	0
T1	5285	5195	0	0
T2	3347	2975	0	0
T3	2588	2531	0	0
T4	4257	4202	0	0
T5	2832	1863	0	0
T6	14165	14042	0	0
T7	10154	10069	0	0
T8	5489	5405	0	0
T9	1192	1131	0	0
T10	60197	60144	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18447268	18060426	0	0
T1	5285	5195	0	0
T2	3347	2975	0	0
T3	2588	2531	0	0
T4	4257	4202	0	0
T5	2832	1863	0	0
T6	14165	14042	0	0
T7	10154	10069	0	0
T8	5489	5405	0	0
T9	1192	1131	0	0
T10	60197	60144	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18447268	18060426	0	0
T1	5285	5195	0	0
T2	3347	2975	0	0
T3	2588	2531	0	0
T4	4257	4202	0	0
T5	2832	1863	0	0
T6	14165	14042	0	0
T7	10154	10069	0	0
T8	5489	5405	0	0
T9	1192	1131	0	0
T10	60197	60144	0	0