Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	39	1	1	100.00
ALWAYS	40	1	1	100.00
ALWAYS	41	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39	1	1
40	1	1
41	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       39
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       40
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       41
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RomAllowActiveState_A	18447268	41932	0	0
RomAllowCheckGoodState_A	18447268	41983	0	0
RomBlockActiveState_A	18447268	27655	0	0
RomBlockCheckGoodState_A	18447268	337486	0	0
RomIntgChkDisFalse_A	18447268	17930612	0	0
RomIntgChkDisTrue_A	18447268	129814	0	0
RstreqChkEsctimeout_A	18447268	3064	0	0
RstreqChkFsmterm_A	18447268	140	0	0
RstreqChkGlbesc_A	18447268	3068	0	0
RstreqChkMainpd_A	18447268	749753	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18447268	41932	0	0
T1	5285	11	0	0
T2	3347	5	0	0
T3	2588	3	0	0
T4	4257	4	0	0
T5	2832	12	0	0
T6	14165	24	0	0
T7	10154	14	0	0
T8	5489	18	0	0
T9	1192	2	0	0
T10	60197	91	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18447268	41983	0	0
T1	5285	11	0	0
T2	3347	5	0	0
T3	2588	3	0	0
T4	4257	4	0	0
T5	2832	13	0	0
T6	14165	24	0	0
T7	10154	14	0	0
T8	5489	18	0	0
T9	1192	2	0	0
T10	60197	91	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18447268	27655	0	0
T27	5832	923	0	0
T31	0	224	0	0
T34	0	2	0	0
T40	18505	0	0	0
T41	30748	0	0	0
T44	2782	0	0	0
T45	2449	0	0	0
T47	1895	0	0	0
T48	1244	0	0	0
T52	0	161	0	0
T53	0	12	0	0
T63	4991	0	0	0
T68	23648	0	0	0
T144	0	276	0	0
T145	0	18	0	0
T146	0	284	0	0
T147	0	249	0	0
T148	0	730	0	0
T149	5989	0	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18447268	337486	0	0
T6	14165	276	0	0
T7	10154	0	0	0
T8	5489	0	0	0
T9	1192	0	0	0
T10	60197	3940	0	0
T14	395238	1581	0	0
T25	0	161	0	0
T26	57733	4095	0	0
T27	0	1095	0	0
T39	56262	4105	0	0
T40	0	321	0	0
T41	0	2260	0	0
T42	3619	0	0	0
T43	10590	0	0	0
T68	0	1471	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18447268	17930612	0	0
T1	5285	5195	0	0
T2	3347	2975	0	0
T3	2588	2531	0	0
T4	4257	4202	0	0
T5	2832	1863	0	0
T6	14165	14042	0	0
T7	10154	10069	0	0
T8	5489	5405	0	0
T9	1192	1131	0	0
T10	60197	55936	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18447268	129814	0	0
T10	60197	4208	0	0
T14	395238	0	0	0
T15	7783	0	0	0
T16	1630	0	0	0
T26	57733	1404	0	0
T27	5832	1923	0	0
T31	0	175	0	0
T39	56262	0	0	0
T42	3619	0	0	0
T43	10590	0	0	0
T52	0	1258	0	0
T68	0	556	0	0
T84	4162	0	0	0
T144	0	1317	0	0
T145	0	651	0	0
T150	0	1267	0	0
T151	0	795	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18447268	3064	0	0
T5	2832	4	0	0
T6	14165	0	0	0
T7	10154	0	0	0
T8	5489	0	0	0
T9	1192	0	0	0
T10	60197	0	0	0
T11	0	1	0	0
T14	395238	40	0	0
T15	0	6	0	0
T27	0	3	0	0
T39	56262	0	0	0
T40	0	9	0	0
T42	3619	0	0	0
T43	10590	0	0	0
T44	0	7	0	0
T45	0	4	0	0
T47	0	5	0	0
T48	0	2	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18447268	140	0	0
T20	13235	20	0	0
T21	0	20	0	0
T22	0	20	0	0
T28	0	40	0	0
T29	0	40	0	0
T30	1166	0	0	0
T31	1579	0	0	0
T32	3067	0	0	0
T33	842	0	0	0
T34	22842	0	0	0
T35	1079	0	0	0
T36	21195	0	0	0
T37	5752	0	0	0
T38	1292	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18447268	3068	0	0
T5	2832	4	0	0
T6	14165	0	0	0
T7	10154	0	0	0
T8	5489	0	0	0
T9	1192	0	0	0
T10	60197	0	0	0
T11	0	1	0	0
T14	395238	40	0	0
T15	0	6	0	0
T27	0	3	0	0
T39	56262	0	0	0
T40	0	9	0	0
T42	3619	0	0	0
T43	10590	0	0	0
T44	0	7	0	0
T45	0	4	0	0
T47	0	5	0	0
T48	0	2	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18447268	749753	0	0
T5	2832	83	0	0
T6	14165	832	0	0
T7	10154	0	0	0
T8	5489	0	0	0
T9	1192	0	0	0
T10	60197	8618	0	0
T14	395238	12004	0	0
T15	0	156	0	0
T26	0	5127	0	0
T27	0	311	0	0
T39	56262	3438	0	0
T40	0	494	0	0
T41	0	2905	0	0
T42	3619	0	0	0
T43	10590	0	0	0