Unified Coverage Report :: Group :: alert_esc_agent_pkg::esc_handshake_complete_cg

Group : alert_esc_agent_pkg::esc_handshake_complete_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
0.00	0.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_alert_esc_agent_0/alert_esc_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
alert_esc_agent_pkg.m_esc_handshake_complete_cg	0.00	1	100	1	64	64

---

Group Instance : alert_esc_agent_pkg.m_esc_handshake_complete_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
0.00	1	100	1	64	64

---

Summary for Group Instance alert_esc_agent_pkg.m_esc_handshake_complete_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	2	0	0.00
Crosses	1	1	0	0.00

Variables for Group Instance alert_esc_agent_pkg.m_esc_handshake_complete_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_handshake_complete	1	1	0	0.00	100	1	1	0
cp_trans_type	1	1	0	0.00	100	1	1	0

Crosses for Group Instance alert_esc_agent_pkg.m_esc_handshake_complete_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
esc_handshake_complete	1	1	0	0.00	100	1	1	0

Summary for Variable cp_handshake_complete

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	1	0	0.00

User Defined Bins for cp_handshake_complete

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
complete	0	1	1

---

Summary for Variable cp_trans_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	1	0	0.00

User Defined Bins for cp_trans_type

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
esc_triggered	0	1	1

---

Summary for Cross esc_handshake_complete

Samples crossed: cp_handshake_complete cp_trans_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	1	0	0.00	1

Automatically Generated Cross Bins for esc_handshake_complete

Uncovered bins

cp_handshake_complete	cp_trans_type	COUNT	AT LEAST	NUMBER	STATUS
*	*	0	1	1