Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	17641	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

21779

1

T1

11

T2

21

T3

20

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	19056	1			T1	31		T2	8		T3	33
values[0x0]	9873	1			T1	9		T2	9		T3	16
values[0x1]	10491	1			T1	17		T2	35		T3	12

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	13838	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

25582

1

T1

26

T2

39

T3

29

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	159	1			T8	1		T12	1		T6	1
valid_sources[0x01]	137	1			T6	3		T43	9		T17	1
valid_sources[0x02]	132	1			T13	15		T6	2		T23	12
valid_sources[0x03]	246	1			T8	5		T42	2		T43	13
valid_sources[0x04]	116	1			T15	1		T47	6		T24	1
valid_sources[0x05]	151	1			T3	1		T12	3		T6	1
valid_sources[0x06]	107	1			T8	2		T14	7		T15	1
valid_sources[0x07]	151	1			T8	2		T5	20		T6	2
valid_sources[0x08]	155	1			T6	3		T47	1		T43	14
valid_sources[0x09]	304	1			T1	15		T3	1		T45	18
valid_sources[0x0a]	116	1			T12	2		T6	3		T47	8
valid_sources[0x0b]	163	1			T15	2		T47	19		T43	9
valid_sources[0x0c]	100	1			T8	1		T6	2		T14	5
valid_sources[0x0d]	117	1			T8	1		T6	1		T14	13
valid_sources[0x0e]	136	1			T8	4		T6	2		T47	17
valid_sources[0x0f]	110	1			T8	3		T6	1		T23	1
valid_sources[0x10]	144	1			T6	1		T14	3		T43	23
valid_sources[0x11]	225	1			T6	1		T15	4		T23	2
valid_sources[0x12]	133	1			T5	4		T6	2		T23	2
valid_sources[0x13]	138	1			T3	2		T8	2		T6	1
valid_sources[0x14]	188	1			T6	2		T43	11		T19	2
valid_sources[0x15]	157	1			T8	1		T4	19		T6	3
valid_sources[0x16]	260	1			T6	1		T14	2		T42	1
valid_sources[0x17]	110	1			T8	4		T6	1		T42	2
valid_sources[0x18]	84	1			T3	4		T8	1		T6	1
valid_sources[0x19]	137	1			T8	3		T43	4		T17	1
valid_sources[0x1a]	127	1			T8	2		T42	3		T43	11
valid_sources[0x1b]	159	1			T45	16		T47	32		T43	9
valid_sources[0x1c]	204	1			T4	34		T6	1		T14	42
valid_sources[0x1d]	115	1			T21	11		T6	2		T42	2
valid_sources[0x1e]	105	1			T2	1		T6	3		T47	2
valid_sources[0x1f]	157	1			T3	1		T8	4		T6	2
valid_sources[0x20]	156	1			T5	2		T6	1		T47	18
valid_sources[0x21]	397	1			T8	1		T7	45		T6	2
valid_sources[0x22]	191	1			T8	1		T10	2		T6	3
valid_sources[0x23]	136	1			T3	1		T5	6		T14	12
valid_sources[0x24]	188	1			T8	4		T12	1		T11	8
valid_sources[0x25]	84	1			T12	1		T24	2		T41	8
valid_sources[0x26]	118	1			T8	1		T6	3		T14	3
valid_sources[0x27]	125	1			T3	1		T8	2		T15	1
valid_sources[0x28]	207	1			T2	2		T5	16		T6	1
valid_sources[0x29]	189	1			T1	4		T9	22		T10	2
valid_sources[0x2a]	108	1			T12	3		T5	9		T6	3
valid_sources[0x2b]	139	1			T8	1		T5	3		T6	1
valid_sources[0x2c]	148	1			T2	2		T6	2		T14	1
valid_sources[0x2d]	167	1			T12	1		T42	1		T16	13
valid_sources[0x2e]	210	1			T2	3		T8	2		T5	1
valid_sources[0x2f]	142	1			T8	1		T15	10		T42	3
valid_sources[0x30]	131	1			T5	2		T13	1		T6	1
valid_sources[0x31]	160	1			T8	1		T7	37		T6	2
valid_sources[0x32]	100	1			T8	1		T5	10		T6	2
valid_sources[0x33]	96	1			T6	3		T15	5		T42	1
valid_sources[0x34]	168	1			T8	4		T6	2		T15	1
valid_sources[0x35]	257	1			T8	2		T14	7		T15	3
valid_sources[0x36]	135	1			T6	2		T43	10		T19	2
valid_sources[0x37]	147	1			T2	1		T8	1		T5	1
valid_sources[0x38]	97	1			T41	12		T42	1		T43	5
valid_sources[0x39]	148	1			T8	3		T6	1		T47	4
valid_sources[0x3a]	148	1			T3	1		T8	2		T5	1
valid_sources[0x3b]	134	1			T6	6		T47	7		T42	1
valid_sources[0x3c]	132	1			T8	4		T42	1		T43	8
valid_sources[0x3d]	163	1			T8	1		T4	17		T5	2
valid_sources[0x3e]	266	1			T21	3		T6	2		T47	21
valid_sources[0x3f]	143	1			T10	1		T43	17		T19	2
valid_sources[0x40]	158	1			T6	5		T23	8		T41	2
valid_sources[0x41]	155	1			T8	1		T6	1		T14	9
valid_sources[0x42]	182	1			T12	1		T47	1		T42	2
valid_sources[0x43]	119	1			T8	1		T12	1		T6	1
valid_sources[0x44]	68	1			T41	2		T42	4		T43	12
valid_sources[0x45]	116	1			T8	1		T6	2		T16	20
valid_sources[0x46]	273	1			T6	1		T42	1		T43	13
valid_sources[0x47]	128	1			T8	1		T12	1		T10	4
valid_sources[0x48]	102	1			T12	1		T21	2		T6	1
valid_sources[0x49]	245	1			T3	2		T6	2		T15	2
valid_sources[0x4a]	260	1			T8	2		T6	2		T42	1
valid_sources[0x4b]	100	1			T12	4		T21	13		T6	1
valid_sources[0x4c]	104	1			T12	1		T14	15		T42	1
valid_sources[0x4d]	166	1			T3	2		T5	1		T47	14
valid_sources[0x4e]	95	1			T6	4		T14	3		T42	1
valid_sources[0x4f]	165	1			T4	34		T12	1		T6	2
valid_sources[0x50]	118	1			T8	3		T5	5		T6	3
valid_sources[0x51]	122	1			T3	3		T6	1		T15	2
valid_sources[0x52]	106	1			T6	1		T43	12		T26	2
valid_sources[0x53]	118	1			T8	1		T47	6		T24	2
valid_sources[0x54]	120	1			T8	1		T12	4		T5	2
valid_sources[0x55]	119	1			T8	1		T6	1		T47	7
valid_sources[0x56]	121	1			T8	1		T6	2		T14	3
valid_sources[0x57]	130	1			T8	1		T12	3		T5	4
valid_sources[0x58]	152	1			T6	3		T14	12		T43	7
valid_sources[0x59]	138	1			T23	3		T47	12		T42	5
valid_sources[0x5a]	185	1			T8	1		T6	2		T15	1
valid_sources[0x5b]	425	1			T3	2		T8	3		T21	5
valid_sources[0x5c]	151	1			T10	1		T14	1		T15	4
valid_sources[0x5d]	123	1			T8	1		T42	1		T43	13
valid_sources[0x5e]	153	1			T3	1		T8	4		T12	1
valid_sources[0x5f]	287	1			T3	1		T5	4		T14	37
valid_sources[0x60]	138	1			T8	1		T12	1		T6	4
valid_sources[0x61]	84	1			T6	1		T42	3		T43	9
valid_sources[0x62]	112	1			T12	2		T43	12		T19	3
valid_sources[0x63]	181	1			T2	3		T8	7		T6	2
valid_sources[0x64]	103	1			T12	1		T47	18		T42	2
valid_sources[0x65]	143	1			T6	1		T47	22		T41	23
valid_sources[0x66]	117	1			T3	3		T8	1		T6	1
valid_sources[0x67]	165	1			T8	2		T5	5		T6	1
valid_sources[0x68]	183	1			T6	4		T15	5		T41	7
valid_sources[0x69]	128	1			T8	3		T12	1		T42	4
valid_sources[0x6a]	349	1			T3	1		T8	3		T14	8
valid_sources[0x6b]	148	1			T8	2		T10	1		T6	5
valid_sources[0x6c]	130	1			T6	2		T15	7		T42	3
valid_sources[0x6d]	95	1			T8	3		T15	1		T42	3
valid_sources[0x6e]	86	1			T42	2		T43	11		T17	1
valid_sources[0x6f]	236	1			T8	1		T14	26		T43	14
valid_sources[0x70]	121	1			T5	16		T6	2		T42	1
valid_sources[0x71]	134	1			T8	1		T6	1		T14	1
valid_sources[0x72]	118	1			T6	1		T42	3		T43	15
valid_sources[0x73]	139	1			T12	1		T5	2		T6	1
valid_sources[0x74]	177	1			T3	1		T47	24		T42	1
valid_sources[0x75]	413	1			T8	3		T21	10		T6	4
valid_sources[0x76]	97	1			T8	2		T10	1		T42	1
valid_sources[0x77]	126	1			T1	7		T8	2		T6	2
valid_sources[0x78]	99	1			T8	1		T43	10		T17	1
valid_sources[0x79]	117	1			T41	8		T43	13		T17	1
valid_sources[0x7a]	131	1			T3	2		T8	5		T6	3
valid_sources[0x7b]	300	1			T8	1		T23	3		T47	12
valid_sources[0x7c]	180	1			T2	3		T3	1		T8	1
valid_sources[0x7d]	196	1			T23	2		T47	22		T24	2
valid_sources[0x7e]	133	1			T8	2		T6	1		T14	6
valid_sources[0x7f]	111	1			T2	10		T8	3		T6	2
valid_sources[0x80]	160	1			T2	1		T6	2		T47	54

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

9585

1

T1

5

T2

5

T3

9

values[0x0]

all_enables

biggest_size

6494

1

T1

3

T2

7

T3

7

values[0x1]

all_enables

biggest_size

5700

1

T1

3

T2

9

T3

4