PWRMGR Simulation Results

Sunday July 21 2024 23:02:06 UTC

GitHub Revision: e971cd9798

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 60538554475599760039478308558126864941531727393021608909386829062452482962039

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwrmgr_smoke 0.770s 30.604us 50 50 100.00
V1 csr_hw_reset pwrmgr_csr_hw_reset 0.710s 64.799us 5 5 100.00
V1 csr_rw pwrmgr_csr_rw 0.720s 16.906us 20 20 100.00
V1 csr_bit_bash pwrmgr_csr_bit_bash 3.560s 316.132us 5 5 100.00
V1 csr_aliasing pwrmgr_csr_aliasing 1.030s 93.715us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwrmgr_csr_mem_rw_with_rand_reset 1.420s 116.224us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwrmgr_csr_rw 0.720s 16.906us 20 20 100.00
pwrmgr_csr_aliasing 1.030s 93.715us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 wakeup pwrmgr_wakeup 1.380s 312.166us 50 50 100.00
V2 control_clks pwrmgr_wakeup 1.380s 312.166us 50 50 100.00
V2 aborted_low_power pwrmgr_aborted_low_power 1.230s 35.486us 50 50 100.00
pwrmgr_lowpower_invalid 0.780s 43.808us 50 50 100.00
V2 reset pwrmgr_reset 1.010s 91.597us 50 50 100.00
pwrmgr_reset_invalid 1.110s 108.622us 50 50 100.00
V2 main_power_glitch_reset pwrmgr_reset 1.010s 91.597us 50 50 100.00
V2 reset_wakeup_race pwrmgr_wakeup_reset 1.730s 368.370us 49 50 98.00
V2 lowpower_wakeup_race pwrmgr_lowpower_wakeup_race 1.310s 286.112us 50 50 100.00
V2 disable_rom_integrity_check pwrmgr_disable_rom_integrity_check 0.950s 63.149us 50 50 100.00
V2 stress_all pwrmgr_stress_all 7.980s 2.188ms 50 50 100.00
V2 intr_test pwrmgr_intr_test 0.670s 23.456us 50 50 100.00
V2 tl_d_oob_addr_access pwrmgr_tl_errors 3.020s 679.367us 20 20 100.00
V2 tl_d_illegal_access pwrmgr_tl_errors 3.020s 679.367us 20 20 100.00
V2 tl_d_outstanding_access pwrmgr_csr_hw_reset 0.710s 64.799us 5 5 100.00
pwrmgr_csr_rw 0.720s 16.906us 20 20 100.00
pwrmgr_csr_aliasing 1.030s 93.715us 5 5 100.00
pwrmgr_same_csr_outstanding 0.940s 48.103us 20 20 100.00
V2 tl_d_partial_access pwrmgr_csr_hw_reset 0.710s 64.799us 5 5 100.00
pwrmgr_csr_rw 0.720s 16.906us 20 20 100.00
pwrmgr_csr_aliasing 1.030s 93.715us 5 5 100.00
pwrmgr_same_csr_outstanding 0.940s 48.103us 20 20 100.00
V2 TOTAL 539 540 99.81
V2S tl_intg_err pwrmgr_tl_intg_err 1.800s 792.655us 20 20 100.00
pwrmgr_sec_cm 1.870s 693.551us 5 5 100.00
V2S prim_count_check pwrmgr_sec_cm 1.870s 693.551us 5 5 100.00
V2S prim_fsm_check pwrmgr_sec_cm 1.870s 693.551us 5 5 100.00
V2S sec_cm_bus_integrity pwrmgr_tl_intg_err 1.800s 792.655us 20 20 100.00
V2S sec_cm_lc_ctrl_intersig_mubi pwrmgr_sec_cm_lc_ctrl_intersig_mubi 3.330s 827.021us 50 50 100.00
V2S sec_cm_rom_ctrl_intersig_mubi pwrmgr_sec_cm_rom_ctrl_intersig_mubi 3.520s 871.043us 50 50 100.00
V2S sec_cm_rstmgr_intersig_mubi pwrmgr_sec_cm_rstmgr_intersig_mubi 1.030s 76.884us 50 50 100.00
V2S sec_cm_esc_rx_clk_bkgn_chk pwrmgr_esc_clk_rst_malfunc 0.700s 29.165us 50 50 100.00
V2S sec_cm_esc_rx_clk_local_esc pwrmgr_sec_cm 1.870s 693.551us 5 5 100.00
V2S sec_cm_fsm_sparse pwrmgr_sec_cm 1.870s 693.551us 5 5 100.00
V2S sec_cm_fsm_terminal pwrmgr_sec_cm 1.870s 693.551us 5 5 100.00
V2S sec_cm_ctrl_flow_global_esc pwrmgr_global_esc 0.700s 77.945us 50 50 100.00
V2S sec_cm_main_pd_rst_local_esc pwrmgr_glitch 0.790s 58.211us 50 50 100.00
V2S sec_cm_ctrl_config_regwen pwrmgr_sec_cm_ctrl_config_regwen 1.460s 288.836us 50 50 100.00
V2S sec_cm_wakeup_config_regwen pwrmgr_csr_rw 0.720s 16.906us 20 20 100.00
V2S sec_cm_reset_config_regwen pwrmgr_csr_rw 0.720s 16.906us 20 20 100.00
V2S TOTAL 375 375 100.00
V3 escalation_timeout pwrmgr_escalation_timeout 1.040s 163.891us 50 50 100.00
V3 stress_all_with_rand_reset pwrmgr_stress_all_with_rand_reset 43.400s 12.808ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1119 1120 99.91

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 12 12 11 91.67
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.95 98.23 96.58 99.44 96.00 96.37 100.00 99.02

Failure Buckets

Past Results