PWRMGR Simulation Results

Monday July 22 2024 23:02:17 UTC

GitHub Revision: 3e0219a2c5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 78193674045195286552709223969981662100934453993551616519215297815848091296886

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.770s	27.330us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.710s	47.314us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.770s	156.681us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.560s	1.321ms	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.080s	178.217us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.690s	58.739us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.770s	156.681us	20	20	100.00
		pwrmgr_csr_aliasing	1.080s	178.217us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.530s	301.612us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.530s	301.612us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	1.040s	32.206us	50	50	100.00
		pwrmgr_lowpower_invalid	0.790s	42.285us	48	50	96.00
V2	reset	pwrmgr_reset	1.070s	102.593us	50	50	100.00
		pwrmgr_reset_invalid	1.140s	105.117us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.070s	102.593us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.520s	329.383us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.430s	291.351us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	1.090s	59.211us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	6.530s	1.962ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.680s	68.015us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.470s	147.107us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.470s	147.107us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.710s	47.314us	5	5	100.00
		pwrmgr_csr_rw	0.770s	156.681us	20	20	100.00
		pwrmgr_csr_aliasing	1.080s	178.217us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.960s	53.032us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.710s	47.314us	5	5	100.00
		pwrmgr_csr_rw	0.770s	156.681us	20	20	100.00
		pwrmgr_csr_aliasing	1.080s	178.217us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.960s	53.032us	20	20	100.00
V2		TOTAL			538	540	99.63
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.790s	204.198us	20	20	100.00
		pwrmgr_sec_cm	1.620s	341.753us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	1.620s	341.753us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	1.620s	341.753us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.790s	204.198us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	3.510s	911.712us	49	50	98.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	3.420s	849.949us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	1.020s	73.998us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.710s	32.624us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	1.620s	341.753us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	1.620s	341.753us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	1.620s	341.753us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.700s	44.101us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.750s	52.781us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.400s	294.593us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.770s	156.681us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.770s	156.681us	20	20	100.00
V2S		TOTAL			374	375	99.73
V3	escalation_timeout	pwrmgr_escalation_timeout	1.050s	161.195us	50	50	100.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	41.330s	12.262ms	50	50	100.00
V3		TOTAL			100	100	100.00
		TOTAL			1117	1120	99.73

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	11	91.67
V2S	9	9	8	88.89
V3	2	2	2	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.92	98.23	96.58	99.44	96.00	96.37	100.00	98.85

Failure Buckets

• UVM_FATAL (pwrmgr_lowpower_invalid_vseq.sv:61) [pwrmgr_lowpower_invalid_vseq] Timed out waiting for state DVWaitFallThrough has 2 failures:

  • Test pwrmgr_lowpower_invalid has 2 failures.

    • 17.pwrmgr_lowpower_invalid.55559550901989267469871303800642713344472636721169308201031699128231931107613
      Line 250, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/17.pwrmgr_lowpower_invalid/latest/run.log

        UVM_FATAL @  37670234 ps: (pwrmgr_lowpower_invalid_vseq.sv:61) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_invalid_vseq] Timed out waiting for state DVWaitFallThrough
        UVM_INFO @  37670234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 30.pwrmgr_lowpower_invalid.23068989115065980404986398494573386670921008026258336299867912654697126055471
      Line 250, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/30.pwrmgr_lowpower_invalid/latest/run.log

        UVM_FATAL @  45695236 ps: (pwrmgr_lowpower_invalid_vseq.sv:61) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_invalid_vseq] Timed out waiting for state DVWaitFallThrough
        UVM_INFO @  45695236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test pwrmgr_sec_cm_lc_ctrl_intersig_mubi has 1 failures.

    • 41.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.21378925073281808879835050866176415800303249136215633996568191767341705985073
      Line 653, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/41.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest/run.log

        UVM_FATAL @ 3000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 3000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 3000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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