PWRMGR Simulation Results

Tuesday July 30 2024 23:02:08 UTC

GitHub Revision: `fdfa12db04`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 101467584611478134588291649782725219255540557286164709436567235390830780957271

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.750s	46.322us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.710s	35.615us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.720s	18.317us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.570s	1.062ms	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	0.860s	32.540us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.410s	57.420us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.720s	18.317us	20	20	100.00
		pwrmgr_csr_aliasing	0.860s	32.540us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	0.910s	88.701us	3	50	6.00
V2	control_clks	pwrmgr_wakeup	0.910s	88.701us	3	50	6.00
V2	aborted_low_power	pwrmgr_aborted_low_power	1.140s	37.380us	50	50	100.00
		pwrmgr_lowpower_invalid	0.790s	80.063us	50	50	100.00
V2	reset	pwrmgr_reset	0.980s	88.906us	50	50	100.00
		pwrmgr_reset_invalid	1.170s	109.901us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	0.980s	88.906us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	0.730s	61.002us	1	50	2.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	0.790s	141.673us	5	50	10.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.940s	55.924us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	1.660s	233.721us	3	50	6.00
V2	intr_test	pwrmgr_intr_test	0.700s	18.138us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.930s	289.620us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.930s	289.620us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.710s	35.615us	5	5	100.00
		pwrmgr_csr_rw	0.720s	18.317us	20	20	100.00
		pwrmgr_csr_aliasing	0.860s	32.540us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.940s	271.935us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.710s	35.615us	5	5	100.00
		pwrmgr_csr_rw	0.720s	18.317us	20	20	100.00
		pwrmgr_csr_aliasing	0.860s	32.540us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.940s	271.935us	20	20	100.00
V2		TOTAL			352	540	65.19
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.650s	182.666us	20	20	100.00
		pwrmgr_sec_cm	1.970s	590.861us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	1.970s	590.861us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	1.970s	590.861us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.650s	182.666us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	0.770s	36.883us	0	50	0.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	0.710s	65.603us	0	50	0.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	0.890s	50.801us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.680s	28.866us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	1.970s	590.861us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	1.970s	590.861us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	1.970s	590.861us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.670s	79.618us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.730s	58.899us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	0.900s	84.971us	3	50	6.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.720s	18.317us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.720s	18.317us	20	20	100.00
V2S		TOTAL			228	375	60.80
V3	escalation_timeout	pwrmgr_escalation_timeout	1.090s	159.881us	50	50	100.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	2.290s	194.353us	0	50	0.00
V3		TOTAL			50	100	50.00
		TOTAL			735	1120	65.62

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	8	66.67
V2S	9	9	6	66.67
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.32	98.23	96.15	99.44	96.00	96.18	100.00	95.25

Failure Buckets

UVM_ERROR (pwrmgr_base_vseq.sv:269) [pwrmgr_repeat_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (* [*] vs * [*]) has 100 failures:

Test pwrmgr_sec_cm_lc_ctrl_intersig_mubi has 50 failures.

0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.14991798322732503697079963596449406689167467941933376577305446442163524252245
Line 279, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest/run.log

  UVM_ERROR @  46004419 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_repeat_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @  46004419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.35528527469649408581093857979308086386007077703012184333215699189716414134041
Line 285, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest/run.log

  UVM_ERROR @ 100599591 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_repeat_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 100599591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 48 more failures.

Test pwrmgr_sec_cm_rom_ctrl_intersig_mubi has 50 failures.

0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.51974698389725500706985941554007255853835871824863854007595257716952464018975
Line 298, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest/run.log

  UVM_ERROR @  32388116 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_repeat_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @  32388116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.16592471471621842975069058600386927606280366154044295430659076250127585218049
Line 275, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest/run.log

  UVM_ERROR @  24817920 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_repeat_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @  24817920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 48 more failures.

UVM_ERROR (pwrmgr_base_vseq.sv:269) [pwrmgr_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (* [*] vs * [*]) has 77 failures:

Test pwrmgr_wakeup_reset has 49 failures.

0.pwrmgr_wakeup_reset.11731002593697540516866133357260784306175709324214324354262956543722179353060
Line 262, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_wakeup_reset/latest/run.log

  UVM_ERROR @  24048423 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @  24048423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.pwrmgr_wakeup_reset.99247210464620016218549243424795407898564116621670712871689817115703636840080
Line 268, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_wakeup_reset/latest/run.log

  UVM_ERROR @  52419092 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @  52419092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 47 more failures.

Test pwrmgr_stress_all_with_rand_reset has 16 failures.

5.pwrmgr_stress_all_with_rand_reset.101390859727719455626354419017577208983407359225742583314585257541753440570600
Line 263, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/5.pwrmgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  39099492 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @  39099492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.pwrmgr_stress_all_with_rand_reset.56250610526367347675678839875637637748794095922590432395027439427439406808986
Line 266, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/7.pwrmgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  30124885 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @  30124885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 14 more failures.

Test pwrmgr_stress_all has 12 failures.

7.pwrmgr_stress_all.51392054008231919682141007835174207066168273686040609874366738162612379783722
Line 309, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/7.pwrmgr_stress_all/latest/run.log

  UVM_ERROR @  39782558 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @  39782558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.pwrmgr_stress_all.12420902421137135751034255955072813034565282292919097023975936859964813966395
Line 353, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/9.pwrmgr_stress_all/latest/run.log

  UVM_ERROR @ 217397134 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 217397134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 10 more failures.

UVM_ERROR (pwrmgr_base_vseq.sv:269) [pwrmgr_wakeup_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (* [*] vs * [*]) has 63 failures:

Test pwrmgr_wakeup has 31 failures.

0.pwrmgr_wakeup.85738802083000270612449216559311013121193203127055413084869366109231014105616
Line 352, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_wakeup/latest/run.log

  UVM_ERROR @  68433736 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @  68433736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.pwrmgr_wakeup.4490029747082375773389376904773658587931987390740855479334058521450268148836
Line 286, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_wakeup/latest/run.log

  UVM_ERROR @  49385574 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @  49385574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 29 more failures.

Test pwrmgr_stress_all_with_rand_reset has 16 failures.

0.pwrmgr_stress_all_with_rand_reset.58560407486671834745052990644452939233516219561469594406217754524155909559816
Line 674, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 134082903 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 134082903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.pwrmgr_stress_all_with_rand_reset.49888576206433400810942918731408963366735325118751231731145089875395824445551
Line 461, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 101383973 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 101383973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 14 more failures.

Test pwrmgr_stress_all has 16 failures.

0.pwrmgr_stress_all.91181453844215855908571007854031695702705000821593611625678144827971969007330
Line 747, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_stress_all/latest/run.log

  UVM_ERROR @ 140490841 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 140490841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.pwrmgr_stress_all.88478409154795696266945968027585450119557334391377408132687352566731758410223
Line 259, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_stress_all/latest/run.log

  UVM_ERROR @  41274641 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @  41274641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 14 more failures.

UVM_ERROR (pwrmgr_base_vseq.sv:269) [pwrmgr_lowpower_wakeup_race_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (* [*] vs * [*]) has 47 failures:

Test pwrmgr_lowpower_wakeup_race has 27 failures.

1.pwrmgr_lowpower_wakeup_race.12448306999682883614721049120637374365764577901420649971615600557981794458853
Line 303, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_lowpower_wakeup_race/latest/run.log

  UVM_ERROR @  33856922 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @  33856922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.pwrmgr_lowpower_wakeup_race.95433512209243715894990598863263208020490821595136881989283139726054604508589
Line 259, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_lowpower_wakeup_race/latest/run.log

  UVM_ERROR @  31575130 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @  31575130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 25 more failures.

Test pwrmgr_stress_all_with_rand_reset has 8 failures.

1.pwrmgr_stress_all_with_rand_reset.30202096010702953974094859650686432874814235530774424503261470277194872333590
Line 373, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 172095832 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 172095832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.pwrmgr_stress_all_with_rand_reset.31888305145803431781703481215533131930934951129065682483352802712590107965291
Line 373, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/4.pwrmgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 151177899 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 151177899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

Test pwrmgr_stress_all has 12 failures.

1.pwrmgr_stress_all.63149861747067832691687793173312231984937150689986497626654348579019646468106
Line 259, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_stress_all/latest/run.log

  UVM_ERROR @  78885299 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @  78885299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.pwrmgr_stress_all.48945267798604597929098476590349084482087817193109596024114819596224684661727
Line 722, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_stress_all/latest/run.log

  UVM_ERROR @ 233721407 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 233721407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 10 more failures.

UVM_ERROR (pwrmgr_base_vseq.sv:269) [pwrmgr_sec_cm_ctrl_config_regwen_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (* [*] vs * [*]) has 33 failures:
- Test pwrmgr_sec_cm_ctrl_config_regwen has 33 failures.
  - 1.pwrmgr_sec_cm_ctrl_config_regwen.51813945082498408478235476298392477750111059999867919955980414783145096994836
    Line 279, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_sec_cm_ctrl_config_regwen/latest/run.log
```
  UVM_ERROR @  84847701 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_sec_cm_ctrl_config_regwen_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @  84847701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.pwrmgr_sec_cm_ctrl_config_regwen.51901876939141028745097372441044892958143970391485023354787895962217087875767
    Line 255, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_sec_cm_ctrl_config_regwen/latest/run.log
```
  UVM_ERROR @  24731396 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_sec_cm_ctrl_config_regwen_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @  24731396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 31 more failures.

UVM_FATAL (pwrmgr_base_vseq.sv:721) [pwrmgr_wakeup_vseq] wake info wait timeout exp:'{reasons:'{d:*}, fall_through:'{d:*}, abort:'{d:*}} actual:'{reasons:'{d:*}, fall_through:'{d:*}, abort:'{d:*}} has 26 failures:

Test pwrmgr_stress_all_with_rand_reset has 8 failures.

3.pwrmgr_stress_all_with_rand_reset.36769084527257639251535767691253249942057561441615091907193611380229846567759
Line 487, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 360606010 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h30}, fall_through:'{d:'h0}, abort:'{d:'h0}}
  UVM_INFO @ 360606010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.pwrmgr_stress_all_with_rand_reset.58467163345872974839363289986798706889556806534193976162059004884674984554245
Line 264, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/6.pwrmgr_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @  52045319 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h20}, fall_through:'{d:'h0}, abort:'{d:'h0}}
  UVM_INFO @  52045319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

Test pwrmgr_wakeup has 16 failures.

6.pwrmgr_wakeup.7886799088370583866659014195934356009921121854676978097976469817799990202690
Line 275, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/6.pwrmgr_wakeup/latest/run.log

  UVM_FATAL @  48974370 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'hb}, fall_through:'{d:'h0}, abort:'{d:'h0}}
  UVM_INFO @  48974370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.pwrmgr_wakeup.30239366011930677986676129193628394844615124081720491250756857427767327574681
Line 263, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/7.pwrmgr_wakeup/latest/run.log

  UVM_FATAL @  53836349 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h22}, fall_through:'{d:'h0}, abort:'{d:'h0}}
  UVM_INFO @  53836349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 14 more failures.

Test pwrmgr_stress_all has 2 failures.

8.pwrmgr_stress_all.95948634256748343169966454766481889793891489116279261419081894842631167323350
Line 370, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/8.pwrmgr_stress_all/latest/run.log

  UVM_FATAL @ 157312038 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h8}, fall_through:'{d:'h0}, abort:'{d:'h0}}
  UVM_INFO @ 157312038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

30.pwrmgr_stress_all.16754623455763055889459002092915590444369659771657427422328667865396860670627
Line 448, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/30.pwrmgr_stress_all/latest/run.log

  UVM_FATAL @ 236612161 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h10}, fall_through:'{d:'h0}, abort:'{d:'h0}}
  UVM_INFO @ 236612161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (pwrmgr_base_vseq.sv:721) [pwrmgr_lowpower_wakeup_race_vseq] wake info wait timeout exp:'{reasons:'{d:*}, fall_through:'{d:*}, abort:'{d:*}} actual:'{reasons:'{d:*}, fall_through:'{d:*}, abort:'{d:*}} has 25 failures:

Test pwrmgr_lowpower_wakeup_race has 18 failures.

0.pwrmgr_lowpower_wakeup_race.114771314313342382535353821322963630120349952888925056783181617288054836488339
Line 286, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_lowpower_wakeup_race/latest/run.log

  UVM_FATAL @  81232187 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h34}, fall_through:'{d:'h0}, abort:'{d:'h0}}
  UVM_INFO @  81232187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.pwrmgr_lowpower_wakeup_race.108696115562652747708715832266770251923032256526717887586350267666011030691641
Line 283, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/4.pwrmgr_lowpower_wakeup_race/latest/run.log

  UVM_FATAL @  83596540 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h0}, fall_through:'{d:'h0}, abort:'{d:'h0}}
  UVM_INFO @  83596540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 16 more failures.

Test pwrmgr_stress_all has 5 failures.

5.pwrmgr_stress_all.19295818476477124118017196348266753612755077801107203831890763501856300058770
Line 286, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/5.pwrmgr_stress_all/latest/run.log

  UVM_FATAL @ 148010838 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h38}, fall_through:'{d:'h0}, abort:'{d:'h0}}
  UVM_INFO @ 148010838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

11.pwrmgr_stress_all.49144304761669758707002975239095067892643372672929370268078834479988110691317
Line 309, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/11.pwrmgr_stress_all/latest/run.log

  UVM_FATAL @  70980514 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h23}, fall_through:'{d:'h0}, abort:'{d:'h0}}
  UVM_INFO @  70980514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test pwrmgr_stress_all_with_rand_reset has 2 failures.

17.pwrmgr_stress_all_with_rand_reset.39915868415260037396933317414385629809547970964032668222928052053737254702964
Line 314, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/17.pwrmgr_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @  70657682 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h3f}, fall_through:'{d:'h0}, abort:'{d:'h0}}
  UVM_INFO @  70657682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

34.pwrmgr_stress_all_with_rand_reset.27777553400799623176852372308961332684205449869137997755502467087535454242480
Line 307, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/34.pwrmgr_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @  76391838 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'hf}, fall_through:'{d:'h0}, abort:'{d:'h0}}
  UVM_INFO @  76391838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (pwrmgr_base_vseq.sv:721) [pwrmgr_sec_cm_ctrl_config_regwen_vseq] wake info wait timeout exp:'{reasons:'{d:*}, fall_through:'{d:*}, abort:'{d:*}} actual:'{reasons:'{d:*}, fall_through:'{d:*}, abort:'{d:*}} has 14 failures:

Test pwrmgr_sec_cm_ctrl_config_regwen has 14 failures.

0.pwrmgr_sec_cm_ctrl_config_regwen.82492255967123584571519769225182473442611694416538045184993356214317102825456
Line 284, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_sec_cm_ctrl_config_regwen/latest/run.log

  UVM_FATAL @  67112221 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_sec_cm_ctrl_config_regwen_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h3e}, fall_through:'{d:'h0}, abort:'{d:'h0}}
  UVM_INFO @  67112221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.pwrmgr_sec_cm_ctrl_config_regwen.9927212958397033547398924860049476216619515442149185656873764492078586848669
Line 377, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/4.pwrmgr_sec_cm_ctrl_config_regwen/latest/run.log

  UVM_FATAL @  84971215 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_sec_cm_ctrl_config_regwen_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h7}, fall_through:'{d:'h0}, abort:'{d:'h0}}
  UVM_INFO @  84971215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 12 more failures.