625f353e9c| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pwrmgr_smoke | 0.810s | 29.621us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pwrmgr_csr_hw_reset | 0.670s | 72.645us | 5 | 5 | 100.00 |
| V1 | csr_rw | pwrmgr_csr_rw | 0.710s | 95.071us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pwrmgr_csr_bit_bash | 3.460s | 564.932us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pwrmgr_csr_aliasing | 1.000s | 159.483us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pwrmgr_csr_mem_rw_with_rand_reset | 1.510s | 55.270us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pwrmgr_csr_rw | 0.710s | 95.071us | 20 | 20 | 100.00 |
| pwrmgr_csr_aliasing | 1.000s | 159.483us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | wakeup | pwrmgr_wakeup | 0.860s | 79.044us | 5 | 50 | 10.00 |
| V2 | control_clks | pwrmgr_wakeup | 0.860s | 79.044us | 5 | 50 | 10.00 |
| V2 | aborted_low_power | pwrmgr_aborted_low_power | 1.150s | 36.315us | 50 | 50 | 100.00 |
| pwrmgr_lowpower_invalid | 0.840s | 44.084us | 50 | 50 | 100.00 | ||
| V2 | reset | pwrmgr_reset | 1.030s | 96.735us | 50 | 50 | 100.00 |
| pwrmgr_reset_invalid | 1.130s | 100.418us | 50 | 50 | 100.00 | ||
| V2 | main_power_glitch_reset | pwrmgr_reset | 1.030s | 96.735us | 50 | 50 | 100.00 |
| V2 | reset_wakeup_race | pwrmgr_wakeup_reset | 0.750s | 40.011us | 1 | 50 | 2.00 |
| V2 | lowpower_wakeup_race | pwrmgr_lowpower_wakeup_race | 1.120s | 125.748us | 4 | 50 | 8.00 |
| V2 | disable_rom_integrity_check | pwrmgr_disable_rom_integrity_check | 0.860s | 65.770us | 50 | 50 | 100.00 |
| V2 | stress_all | pwrmgr_stress_all | 1.150s | 214.250us | 3 | 50 | 6.00 |
| V2 | intr_test | pwrmgr_intr_test | 0.680s | 19.196us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pwrmgr_tl_errors | 2.540s | 242.645us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pwrmgr_tl_errors | 2.540s | 242.645us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pwrmgr_csr_hw_reset | 0.670s | 72.645us | 5 | 5 | 100.00 |
| pwrmgr_csr_rw | 0.710s | 95.071us | 20 | 20 | 100.00 | ||
| pwrmgr_csr_aliasing | 1.000s | 159.483us | 5 | 5 | 100.00 | ||
| pwrmgr_same_csr_outstanding | 1.010s | 126.761us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pwrmgr_csr_hw_reset | 0.670s | 72.645us | 5 | 5 | 100.00 |
| pwrmgr_csr_rw | 0.710s | 95.071us | 20 | 20 | 100.00 | ||
| pwrmgr_csr_aliasing | 1.000s | 159.483us | 5 | 5 | 100.00 | ||
| pwrmgr_same_csr_outstanding | 1.010s | 126.761us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 353 | 540 | 65.37 | |||
| V2S | tl_intg_err | pwrmgr_tl_intg_err | 1.790s | 211.476us | 20 | 20 | 100.00 |
| pwrmgr_sec_cm | 2.180s | 609.558us | 5 | 5 | 100.00 | ||
| V2S | prim_count_check | pwrmgr_sec_cm | 2.180s | 609.558us | 5 | 5 | 100.00 |
| V2S | prim_fsm_check | pwrmgr_sec_cm | 2.180s | 609.558us | 5 | 5 | 100.00 |
| V2S | sec_cm_bus_integrity | pwrmgr_tl_intg_err | 1.790s | 211.476us | 20 | 20 | 100.00 |
| V2S | sec_cm_lc_ctrl_intersig_mubi | pwrmgr_sec_cm_lc_ctrl_intersig_mubi | 0.790s | 66.640us | 0 | 50 | 0.00 |
| V2S | sec_cm_rom_ctrl_intersig_mubi | pwrmgr_sec_cm_rom_ctrl_intersig_mubi | 0.760s | 147.428us | 0 | 50 | 0.00 |
| V2S | sec_cm_rstmgr_intersig_mubi | pwrmgr_sec_cm_rstmgr_intersig_mubi | 0.980s | 71.969us | 50 | 50 | 100.00 |
| V2S | sec_cm_esc_rx_clk_bkgn_chk | pwrmgr_esc_clk_rst_malfunc | 0.690s | 28.707us | 50 | 50 | 100.00 |
| V2S | sec_cm_esc_rx_clk_local_esc | pwrmgr_sec_cm | 2.180s | 609.558us | 5 | 5 | 100.00 |
| V2S | sec_cm_fsm_sparse | pwrmgr_sec_cm | 2.180s | 609.558us | 5 | 5 | 100.00 |
| V2S | sec_cm_fsm_terminal | pwrmgr_sec_cm | 2.180s | 609.558us | 5 | 5 | 100.00 |
| V2S | sec_cm_ctrl_flow_global_esc | pwrmgr_global_esc | 0.670s | 49.982us | 50 | 50 | 100.00 |
| V2S | sec_cm_main_pd_rst_local_esc | pwrmgr_glitch | 0.700s | 62.417us | 50 | 50 | 100.00 |
| V2S | sec_cm_ctrl_config_regwen | pwrmgr_sec_cm_ctrl_config_regwen | 0.930s | 90.603us | 4 | 50 | 8.00 |
| V2S | sec_cm_wakeup_config_regwen | pwrmgr_csr_rw | 0.710s | 95.071us | 20 | 20 | 100.00 |
| V2S | sec_cm_reset_config_regwen | pwrmgr_csr_rw | 0.710s | 95.071us | 20 | 20 | 100.00 |
| V2S | TOTAL | 229 | 375 | 61.07 | |||
| V3 | escalation_timeout | pwrmgr_escalation_timeout | 1.080s | 605.680us | 50 | 50 | 100.00 |
| V3 | stress_all_with_rand_reset | pwrmgr_stress_all_with_rand_reset | 2.010s | 221.669us | 0 | 50 | 0.00 |
| V3 | TOTAL | 50 | 100 | 50.00 | |||
| TOTAL | 737 | 1120 | 65.80 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 12 | 12 | 8 | 66.67 |
| V2S | 9 | 9 | 6 | 66.67 |
| V3 | 2 | 2 | 1 | 50.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.28 | 98.23 | 96.15 | 99.44 | 96.00 | 96.18 | 100.00 | 94.93 |
UVM_ERROR (pwrmgr_base_vseq.sv:269) [pwrmgr_repeat_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (* [*] vs * [*]) has 100 failures:
0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.24961426187298536271532365121529826594160155973968461631328513316255674742039
Line 270, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest/run.log
UVM_ERROR @ 54851503 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_repeat_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 54851503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1084030527893454925368556802291621340645078340550603004694040224160447152051
Line 273, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest/run.log
UVM_ERROR @ 66676633 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_repeat_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 66676633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 48 more failures.
0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.106337338605607329378972468350779229054440495196138113723493347105718439221491
Line 263, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest/run.log
UVM_ERROR @ 31326571 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_repeat_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 31326571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.54769390950864490677707529158518507523329474294530918334475566724807877729228
Line 293, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest/run.log
UVM_ERROR @ 141998428 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_repeat_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 141998428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 48 more failures.
UVM_ERROR (pwrmgr_base_vseq.sv:269) [pwrmgr_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (* [*] vs * [*]) has 76 failures:
0.pwrmgr_wakeup_reset.82571900968720409829790792323746902646567399621069729423852600999504574609169
Line 267, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_wakeup_reset/latest/run.log
UVM_ERROR @ 23871648 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 23871648 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.pwrmgr_wakeup_reset.70481321090311045471094438677160802398044541901730957764733116486605276198553
Line 261, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_wakeup_reset/latest/run.log
UVM_ERROR @ 33138845 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 33138845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 47 more failures.
0.pwrmgr_stress_all_with_rand_reset.65418217745248683469032426430202727827794713342659262775678108483082351857399
Line 308, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 90610014 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 90610014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.pwrmgr_stress_all_with_rand_reset.55371318610197970527913595029831616995983610355944186812990981732934066415533
Line 264, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/4.pwrmgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 37363355 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 37363355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 12 more failures.
0.pwrmgr_stress_all.52820530287375878906290782309378045497284607034287224315943323646441787902147
Line 285, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_stress_all/latest/run.log
UVM_ERROR @ 105441983 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 105441983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.pwrmgr_stress_all.102560264219539370479790741790497573534411807714869676752960937702734681687541
Line 414, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/5.pwrmgr_stress_all/latest/run.log
UVM_ERROR @ 94067384 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 94067384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 11 more failures.
UVM_ERROR (pwrmgr_base_vseq.sv:269) [pwrmgr_wakeup_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (* [*] vs * [*]) has 58 failures:
1.pwrmgr_stress_all.80158884192000330950788046783631580939593617911659785931413005404002119102031
Line 372, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_stress_all/latest/run.log
UVM_ERROR @ 71332259 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 71332259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.pwrmgr_stress_all.53474088741134075236009759696397704458419859546239056944190234493041381426649
Line 514, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/13.pwrmgr_stress_all/latest/run.log
UVM_ERROR @ 128272360 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 128272360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 10 more failures.
2.pwrmgr_wakeup.3056397868660721921398296455116424911500533691026517914863019646589324511283
Line 279, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_wakeup/latest/run.log
UVM_ERROR @ 23022682 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 23022682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.pwrmgr_wakeup.8216344001464186648956743560216602889433838476478026719196273198821190907903
Line 293, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_wakeup/latest/run.log
UVM_ERROR @ 105281886 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 105281886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 28 more failures.
6.pwrmgr_stress_all_with_rand_reset.94129868210968474483697675801536289494134776004577332625448483435101653527173
Line 307, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/6.pwrmgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 71831749 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 71831749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.pwrmgr_stress_all_with_rand_reset.20753873830623607744503859933599212782959231339783632167986132535025309398871
Line 264, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/7.pwrmgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 56816133 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 56816133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 14 more failures.
UVM_ERROR (pwrmgr_base_vseq.sv:269) [pwrmgr_lowpower_wakeup_race_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (* [*] vs * [*]) has 52 failures:
1.pwrmgr_stress_all_with_rand_reset.57834136261998433826157904859353605857123064527794109484723258786204981285569
Line 331, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 109897713 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 109897713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.pwrmgr_stress_all_with_rand_reset.46986645005488196265348900122131061639622343477815848408143647615418053719508
Line 440, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 101575804 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 101575804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 10 more failures.
4.pwrmgr_lowpower_wakeup_race.40049591167790502110690938463302227786083836530928752884747257299113283395451
Line 451, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/4.pwrmgr_lowpower_wakeup_race/latest/run.log
UVM_ERROR @ 97763603 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 97763603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.pwrmgr_lowpower_wakeup_race.45203011145164097946692619762080879231300158320231921167129964924827890496351
Line 277, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/5.pwrmgr_lowpower_wakeup_race/latest/run.log
UVM_ERROR @ 126795170 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 126795170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 26 more failures.
7.pwrmgr_stress_all.114909481796315553915897842705346826956866246611047227492130315377595295595309
Line 359, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/7.pwrmgr_stress_all/latest/run.log
UVM_ERROR @ 162620665 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 162620665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.pwrmgr_stress_all.5001982743984150459098434852614741903616477789770356820058627978156591522342
Line 258, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/9.pwrmgr_stress_all/latest/run.log
UVM_ERROR @ 41100390 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 41100390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 10 more failures.
UVM_ERROR (pwrmgr_base_vseq.sv:269) [pwrmgr_sec_cm_ctrl_config_regwen_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (* [*] vs * [*]) has 36 failures:
1.pwrmgr_sec_cm_ctrl_config_regwen.8682539136534623544921705519366148485767459872741737819812620119339698449764
Line 285, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_sec_cm_ctrl_config_regwen/latest/run.log
UVM_ERROR @ 66524686 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_sec_cm_ctrl_config_regwen_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 66524686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.pwrmgr_sec_cm_ctrl_config_regwen.8268026044714651262226890585372888694261925684144988115335122501324129517356
Line 298, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_sec_cm_ctrl_config_regwen/latest/run.log
UVM_ERROR @ 37039510 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_sec_cm_ctrl_config_regwen_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 37039510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 34 more failures.
UVM_FATAL (pwrmgr_base_vseq.sv:721) [pwrmgr_lowpower_wakeup_race_vseq] wake info wait timeout exp:'{reasons:'{d:*}, fall_through:'{d:*}, abort:'{d:*}} actual:'{reasons:'{d:*}, fall_through:'{d:*}, abort:'{d:*}} has 26 failures:
0.pwrmgr_lowpower_wakeup_race.95989622309118876158948484224460968543990377608174839698605462354708057080402
Line 333, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_lowpower_wakeup_race/latest/run.log
UVM_FATAL @ 80937748 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h3a}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 80937748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.pwrmgr_lowpower_wakeup_race.105316979671948672850162263236718580444279155404457318828223440984075467814102
Line 480, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_lowpower_wakeup_race/latest/run.log
UVM_FATAL @ 125747738 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h1f}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 125747738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 16 more failures.
4.pwrmgr_stress_all.105324909477016987703370743260095217822580172083975333403206790699679817164598
Line 278, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/4.pwrmgr_stress_all/latest/run.log
UVM_FATAL @ 56265304 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'hf}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 56265304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.pwrmgr_stress_all.19642486261822668416352482856211883376745737355143439477168067248323356258906
Line 267, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/8.pwrmgr_stress_all/latest/run.log
UVM_FATAL @ 128256257 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h10}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 128256257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
23.pwrmgr_stress_all_with_rand_reset.71861132963038077439517987455333292209902968943517483780522685867470843539195
Line 302, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/23.pwrmgr_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 74638217 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h2c}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 74638217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
28.pwrmgr_stress_all_with_rand_reset.43662249778993236675180926113248506483232246245023324730035106679580379396206
Line 291, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/28.pwrmgr_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 87345595 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h3f}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 87345595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (pwrmgr_base_vseq.sv:721) [pwrmgr_wakeup_vseq] wake info wait timeout exp:'{reasons:'{d:*}, fall_through:'{d:*}, abort:'{d:*}} actual:'{reasons:'{d:*}, fall_through:'{d:*}, abort:'{d:*}} has 25 failures:
0.pwrmgr_wakeup.81889835643388398530290184545235573010041534218186221463250970983468001889846
Line 278, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_wakeup/latest/run.log
UVM_FATAL @ 44287960 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h0}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 44287960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.pwrmgr_wakeup.24472740226291329779552738506337781047945702713321852320903285953514853349731
Line 266, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_wakeup/latest/run.log
UVM_FATAL @ 111150724 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h20}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 111150724 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 13 more failures.
2.pwrmgr_stress_all_with_rand_reset.3726167240205639469632991063279254628032993937191102443893532916888624602400
Line 287, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 391579213 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h0}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 391579213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.pwrmgr_stress_all_with_rand_reset.57031004627389078129264037143862700313203399905797005295023363054415914501346
Line 319, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/10.pwrmgr_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 104510121 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h28}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 104510121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
2.pwrmgr_stress_all.87546694676596810111258176792156028236422241087462473115984423397858457589442
Line 299, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_stress_all/latest/run.log
UVM_FATAL @ 107807180 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h11}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 107807180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.pwrmgr_stress_all.4067601830205909832381384655510109666257008390661632141241286789529996890619
Line 338, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_stress_all/latest/run.log
UVM_FATAL @ 101789312 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'hc}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 101789312 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_FATAL (pwrmgr_base_vseq.sv:721) [pwrmgr_sec_cm_ctrl_config_regwen_vseq] wake info wait timeout exp:'{reasons:'{d:*}, fall_through:'{d:*}, abort:'{d:*}} actual:'{reasons:'{d:*}, fall_through:'{d:*}, abort:'{d:*}} has 10 failures:
0.pwrmgr_sec_cm_ctrl_config_regwen.75220214886315602588581283170671687769546553047690261204665804859665743221434
Line 276, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_sec_cm_ctrl_config_regwen/latest/run.log
UVM_FATAL @ 46076146 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_sec_cm_ctrl_config_regwen_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'he}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 46076146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.pwrmgr_sec_cm_ctrl_config_regwen.51080726598262262458708751045894880460406757015862147421946491794226475970563
Line 281, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/7.pwrmgr_sec_cm_ctrl_config_regwen/latest/run.log
UVM_FATAL @ 70423657 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_sec_cm_ctrl_config_regwen_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h29}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 70423657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.