Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	357051	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

141293

1

T1

14

T2

11

T3

7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	259363	1			T1	28		T2	46		T3	15
values[0x0]	119134	1			T1	8		T2	15		T3	5
values[0x1]	119847	1			T1	2		T2	15		T3	11

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	282756	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

215588

1

T1

17

T2

34

T3

16

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1913	1			T2	1		T37	2		T99	2
valid_sources[0x01]	2711	1			T1	1		T33	1		T37	1
valid_sources[0x02]	2530	1			T14	2		T16	2		T161	4
valid_sources[0x03]	2091	1			T36	1		T40	1		T16	1
valid_sources[0x04]	1567	1			T35	1		T16	2		T99	1
valid_sources[0x05]	2058	1			T36	2		T29	1		T37	2
valid_sources[0x06]	2102	1			T10	1		T14	3		T37	1
valid_sources[0x07]	1496	1			T1	1		T10	1		T14	2
valid_sources[0x08]	2828	1			T35	1		T39	1		T17	3
valid_sources[0x09]	1690	1			T2	1		T35	1		T16	2
valid_sources[0x0a]	1584	1			T1	1		T2	6		T99	2
valid_sources[0x0b]	2833	1			T1	2		T9	21		T27	2
valid_sources[0x0c]	1664	1			T10	1		T14	1		T37	1
valid_sources[0x0d]	2635	1			T3	2		T35	1		T99	1
valid_sources[0x0e]	2595	1			T1	3		T37	2		T27	9
valid_sources[0x0f]	1610	1			T99	1		T161	2		T17	1
valid_sources[0x10]	1956	1			T14	1		T37	1		T161	2
valid_sources[0x11]	2946	1			T14	2		T11	1		T16	1
valid_sources[0x12]	1755	1			T1	1		T14	1		T33	1
valid_sources[0x13]	1813	1			T2	3		T14	1		T161	3
valid_sources[0x14]	1758	1			T13	2		T99	3		T118	2
valid_sources[0x15]	1520	1			T14	1		T161	2		T17	2
valid_sources[0x16]	2203	1			T14	7		T29	2		T37	1
valid_sources[0x17]	1545	1			T1	1		T33	2		T18	1
valid_sources[0x18]	2516	1			T2	2		T14	2		T99	1
valid_sources[0x19]	2021	1			T29	1		T16	1		T27	3
valid_sources[0x1a]	1512	1			T3	1		T6	1		T14	3
valid_sources[0x1b]	1655	1			T16	1		T99	1		T17	3
valid_sources[0x1c]	1636	1			T14	5		T36	1		T29	4
valid_sources[0x1d]	1716	1			T14	1		T29	3		T37	1
valid_sources[0x1e]	1733	1			T2	1		T3	2		T14	5
valid_sources[0x1f]	1987	1			T2	1		T10	2		T13	3
valid_sources[0x20]	2711	1			T1	1		T7	15		T9	5
valid_sources[0x21]	1951	1			T16	3		T118	2		T161	6
valid_sources[0x22]	3134	1			T9	5		T36	4		T17	4
valid_sources[0x23]	1574	1			T29	1		T39	2		T17	1
valid_sources[0x24]	1663	1			T2	2		T3	1		T37	2
valid_sources[0x25]	2122	1			T14	1		T37	3		T16	1
valid_sources[0x26]	1783	1			T2	3		T14	5		T35	1
valid_sources[0x27]	1427	1			T3	1		T14	1		T17	1
valid_sources[0x28]	1923	1			T37	3		T39	2		T17	3
valid_sources[0x29]	1414	1			T14	1		T37	1		T16	1
valid_sources[0x2a]	1452	1			T36	1		T37	1		T161	1
valid_sources[0x2b]	1561	1			T14	1		T99	2		T39	4
valid_sources[0x2c]	1801	1			T37	3		T99	1		T39	2
valid_sources[0x2d]	1460	1			T14	1		T36	2		T29	3
valid_sources[0x2e]	1626	1			T13	3		T36	1		T37	1
valid_sources[0x2f]	1506	1			T14	2		T37	1		T16	1
valid_sources[0x30]	1605	1			T3	1		T36	2		T99	1
valid_sources[0x31]	1693	1			T5	13		T14	2		T37	1
valid_sources[0x32]	2976	1			T10	2		T14	1		T37	2
valid_sources[0x33]	2140	1			T14	1		T17	2		T117	4
valid_sources[0x34]	3427	1			T2	2		T36	6		T37	1
valid_sources[0x35]	1581	1			T2	1		T14	1		T29	5
valid_sources[0x36]	3815	1			T1	1		T14	2		T16	2
valid_sources[0x37]	1677	1			T36	1		T16	2		T17	3
valid_sources[0x38]	1589	1			T14	1		T37	3		T99	1
valid_sources[0x39]	1589	1			T3	2		T14	1		T29	1
valid_sources[0x3a]	2882	1			T14	2		T33	1		T17	1
valid_sources[0x3b]	2002	1			T2	1		T14	1		T118	4
valid_sources[0x3c]	1467	1			T2	2		T3	2		T14	1
valid_sources[0x3d]	1514	1			T14	1		T33	1		T37	1
valid_sources[0x3e]	1628	1			T16	2		T99	1		T118	4
valid_sources[0x3f]	1431	1			T1	1		T14	1		T29	4
valid_sources[0x40]	1682	1			T16	1		T161	2		T39	1
valid_sources[0x41]	1669	1			T14	2		T35	1		T37	1
valid_sources[0x42]	1714	1			T14	3		T37	1		T16	1
valid_sources[0x43]	1733	1			T1	1		T99	3		T161	1
valid_sources[0x44]	1893	1			T14	2		T36	4		T16	1
valid_sources[0x45]	1651	1			T10	1		T29	1		T37	1
valid_sources[0x46]	1686	1			T9	5		T36	3		T29	3
valid_sources[0x47]	1942	1			T36	5		T99	1		T118	7
valid_sources[0x48]	1694	1			T1	2		T2	1		T14	1
valid_sources[0x49]	1590	1			T37	1		T17	2		T28	10
valid_sources[0x4a]	1316	1			T1	1		T33	1		T17	3
valid_sources[0x4b]	1979	1			T14	1		T37	1		T39	1
valid_sources[0x4c]	2107	1			T2	1		T29	1		T99	1
valid_sources[0x4d]	1658	1			T37	2		T16	1		T99	3
valid_sources[0x4e]	1551	1			T7	21		T14	2		T16	1
valid_sources[0x4f]	1553	1			T14	6		T29	1		T99	2
valid_sources[0x50]	1683	1			T9	19		T17	4		T117	2
valid_sources[0x51]	1427	1			T2	1		T3	1		T9	2
valid_sources[0x52]	1713	1			T32	1		T14	1		T33	1
valid_sources[0x53]	1888	1			T1	1		T99	2		T38	121
valid_sources[0x54]	1654	1			T3	2		T14	1		T16	1
valid_sources[0x55]	1687	1			T37	1		T99	1		T17	5
valid_sources[0x56]	2022	1			T118	6		T39	1		T17	9
valid_sources[0x57]	1831	1			T1	1		T37	1		T16	1
valid_sources[0x58]	1815	1			T10	1		T33	1		T29	3
valid_sources[0x59]	1547	1			T37	1		T17	1		T117	4
valid_sources[0x5a]	2532	1			T8	1		T14	2		T37	2
valid_sources[0x5b]	1513	1			T7	52		T10	1		T36	2
valid_sources[0x5c]	1595	1			T1	1		T14	1		T33	1
valid_sources[0x5d]	1669	1			T14	2		T161	3		T17	1
valid_sources[0x5e]	2700	1			T1	1		T14	1		T37	2
valid_sources[0x5f]	1689	1			T16	1		T161	2		T17	4
valid_sources[0x60]	1622	1			T37	3		T161	2		T17	1
valid_sources[0x61]	1731	1			T35	1		T39	1		T17	2
valid_sources[0x62]	2622	1			T35	1		T99	1		T161	2
valid_sources[0x63]	1313	1			T36	2		T37	3		T27	1
valid_sources[0x64]	1720	1			T10	1		T36	1		T99	3
valid_sources[0x65]	1734	1			T14	1		T16	3		T27	1
valid_sources[0x66]	1593	1			T3	1		T14	1		T35	2
valid_sources[0x67]	1672	1			T37	1		T16	1		T99	1
valid_sources[0x68]	1649	1			T14	3		T36	2		T16	1
valid_sources[0x69]	1735	1			T33	2		T16	1		T161	1
valid_sources[0x6a]	2735	1			T29	3		T27	1		T17	8
valid_sources[0x6b]	1518	1			T2	1		T33	1		T35	1
valid_sources[0x6c]	1617	1			T2	1		T14	5		T36	2
valid_sources[0x6d]	1979	1			T5	8		T14	2		T16	1
valid_sources[0x6e]	2056	1			T2	1		T14	1		T36	1
valid_sources[0x6f]	3083	1			T2	1		T36	1		T37	5
valid_sources[0x70]	1635	1			T1	1		T2	1		T14	1
valid_sources[0x71]	3113	1			T14	1		T99	1		T39	3
valid_sources[0x72]	1997	1			T2	3		T35	1		T36	1
valid_sources[0x73]	1547	1			T29	1		T99	2		T161	1
valid_sources[0x74]	2466	1			T17	3		T117	3		T162	1
valid_sources[0x75]	1534	1			T16	1		T99	1		T17	1
valid_sources[0x76]	2092	1			T29	2		T37	1		T17	2
valid_sources[0x77]	1701	1			T1	1		T36	1		T37	2
valid_sources[0x78]	2003	1			T5	14		T14	1		T36	1
valid_sources[0x79]	1571	1			T14	3		T37	1		T27	1
valid_sources[0x7a]	3047	1			T10	1		T14	2		T37	1
valid_sources[0x7b]	1759	1			T14	1		T36	3		T37	1
valid_sources[0x7c]	1602	1			T14	2		T37	1		T99	1
valid_sources[0x7d]	1928	1			T14	3		T36	4		T99	1
valid_sources[0x7e]	2013	1			T2	4		T3	1		T16	1
valid_sources[0x7f]	2022	1			T9	16		T10	2		T37	1
valid_sources[0x80]	1779	1			T3	1		T37	2		T16	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

70296

1

T1

12

T2

6

T3

5

values[0x0]

all_enables

biggest_size

45455

1

T1

2

T2

3

T3

2

values[0x1]

all_enables

biggest_size

25542

1

T2

2

T4

9

T5

4