Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

32                      
33         1/1            always_comb reset_or_disable = !rst_slow_ni || disable_sva;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T33,T44,T42

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	16543113	4486	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	16543113	193198	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	16543113	6814617	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	16543113	193200	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	16543113	4486	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	16543113	193198	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	16543113	6814617	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	16543113	193200	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16543113	4486	0	0
T1	2218	1	0	0
T2	2947	0	0	0
T3	1700	0	0	0
T4	8026	1	0	0
T5	2030	0	0	0
T6	853	0	0	0
T7	20080	0	0	0
T8	1351	0	0	0
T9	4517	5	0	0
T10	1772	0	0	0
T17	0	6	0	0
T28	0	20	0	0
T33	0	3	0	0
T35	0	1	0	0
T39	0	5	0	0
T116	0	14	0	0
T117	0	21	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16543113	193198	0	0
T1	2218	9	0	0
T2	2947	0	0	0
T3	1700	0	0	0
T4	8026	92	0	0
T5	2030	0	0	0
T6	853	0	0	0
T7	20080	0	0	0
T8	1351	0	0	0
T9	4517	80	0	0
T10	1772	0	0	0
T17	0	178	0	0
T28	0	403	0	0
T33	0	282	0	0
T35	0	14	0	0
T39	0	128	0	0
T116	0	652	0	0
T117	0	1286	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16543113	6814617	0	0
T1	2218	1412	0	0
T2	2947	0	0	0
T3	1700	0	0	0
T4	8026	3408	0	0
T5	2030	783	0	0
T6	853	0	0	0
T7	20080	9433	0	0
T8	1351	0	0	0
T9	4517	1939	0	0
T10	1772	419	0	0
T33	0	293	0	0
T34	0	8119	0	0
T35	0	1024	0	0
T36	0	2683	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16543113	193200	0	0
T1	2218	9	0	0
T2	2947	0	0	0
T3	1700	0	0	0
T4	8026	92	0	0
T5	2030	0	0	0
T6	853	0	0	0
T7	20080	0	0	0
T8	1351	0	0	0
T9	4517	80	0	0
T10	1772	0	0	0
T17	0	178	0	0
T28	0	403	0	0
T33	0	282	0	0
T35	0	14	0	0
T39	0	128	0	0
T116	0	652	0	0
T117	0	1286	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16543113	4486	0	0
T1	2218	1	0	0
T2	2947	0	0	0
T3	1700	0	0	0
T4	8026	1	0	0
T5	2030	0	0	0
T6	853	0	0	0
T7	20080	0	0	0
T8	1351	0	0	0
T9	4517	5	0	0
T10	1772	0	0	0
T17	0	6	0	0
T28	0	20	0	0
T33	0	3	0	0
T35	0	1	0	0
T39	0	5	0	0
T116	0	14	0	0
T117	0	21	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16543113	193198	0	0
T1	2218	9	0	0
T2	2947	0	0	0
T3	1700	0	0	0
T4	8026	92	0	0
T5	2030	0	0	0
T6	853	0	0	0
T7	20080	0	0	0
T8	1351	0	0	0
T9	4517	80	0	0
T10	1772	0	0	0
T17	0	178	0	0
T28	0	403	0	0
T33	0	282	0	0
T35	0	14	0	0
T39	0	128	0	0
T116	0	652	0	0
T117	0	1286	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16543113	6814617	0	0
T1	2218	1412	0	0
T2	2947	0	0	0
T3	1700	0	0	0
T4	8026	3408	0	0
T5	2030	783	0	0
T6	853	0	0	0
T7	20080	9433	0	0
T8	1351	0	0	0
T9	4517	1939	0	0
T10	1772	419	0	0
T33	0	293	0	0
T34	0	8119	0	0
T35	0	1024	0	0
T36	0	2683	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16543113	193200	0	0
T1	2218	9	0	0
T2	2947	0	0	0
T3	1700	0	0	0
T4	8026	92	0	0
T5	2030	0	0	0
T6	853	0	0	0
T7	20080	0	0	0
T8	1351	0	0	0
T9	4517	80	0	0
T10	1772	0	0	0
T17	0	178	0	0
T28	0	403	0	0
T33	0	282	0	0
T35	0	14	0	0
T39	0	128	0	0
T116	0	652	0	0
T117	0	1286	0	0