Unified Coverage Report :: Module :: pwrmgr_clock_enables_sva_if

Module : pwrmgr_clock_enables_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_clock_enables_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_clock_enables_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_clock_enables_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_clock_enables_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	30	1	1	100.00
ALWAYS	37	1	1	100.00

29                      
30         1/1            always_comb reset_or_disable = !rst_ni || disable_sva;
           Tests:       T1 T2 T3 
31                      
32                        sequence transitionUp_S; slow_state == pwrmgr_pkg::SlowPwrStateReqPwrUp; endsequence
33                      
34                        sequence transitionDown_S; slow_state == pwrmgr_pkg::SlowPwrStatePwrClampOn; endsequence
35                      
36                        bit fast_is_active;
37         1/1            always_comb fast_is_active = fast_state == pwrmgr_pkg::FastPwrStateActive;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : pwrmgr_clock_enables_sva_if

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       30
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T33,T44,T42

 LINE       37
 EXPRESSION (fast_state == FastPwrStateActive)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_clock_enables_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CoreClkPwrDown_A	3497557	9705	0	0
CoreClkPwrUp_A	3497557	120921	0	0
IoClkPwrDown_A	3497557	9705	0	0
IoClkPwrUp_A	3497557	120921	0	0
UsbClkActive_A	3497557	2267	0	0
UsbClkPwrDown_A	3497557	9705	0	0
UsbClkPwrUp_A	3497557	120921	0	0

CoreClkPwrDown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3497557	9705	0	0
T1	202	1	0	0
T2	426	0	0	0
T3	740	0	0	0
T4	824	4	0	0
T5	159	0	0	0
T6	267	0	0	0
T7	2157	10	0	0
T8	223	0	0	0
T9	2684	6	0	0
T10	551	1	0	0
T34	0	9	0	0
T35	0	1	0	0
T36	0	7	0	0
T99	0	4	0	0
T118	0	3	0	0

CoreClkPwrUp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3497557	120921	0	0
T1	202	9	0	0
T2	426	0	0	0
T3	740	0	0	0
T4	824	28	0	0
T5	159	0	0	0
T6	267	0	0	0
T7	2157	80	0	0
T8	223	0	0	0
T9	2684	104	0	0
T10	551	13	0	0
T33	0	35	0	0
T34	0	73	0	0
T35	0	10	0	0
T36	0	88	0	0
T99	0	37	0	0

IoClkPwrDown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3497557	9705	0	0
T1	202	1	0	0
T2	426	0	0	0
T3	740	0	0	0
T4	824	4	0	0
T5	159	0	0	0
T6	267	0	0	0
T7	2157	10	0	0
T8	223	0	0	0
T9	2684	6	0	0
T10	551	1	0	0
T34	0	9	0	0
T35	0	1	0	0
T36	0	7	0	0
T99	0	4	0	0
T118	0	3	0	0

IoClkPwrUp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3497557	120921	0	0
T1	202	9	0	0
T2	426	0	0	0
T3	740	0	0	0
T4	824	28	0	0
T5	159	0	0	0
T6	267	0	0	0
T7	2157	80	0	0
T8	223	0	0	0
T9	2684	104	0	0
T10	551	13	0	0
T33	0	35	0	0
T34	0	73	0	0
T35	0	10	0	0
T36	0	88	0	0
T99	0	37	0	0

UsbClkActive_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3497557	2267	0	0
T5	159	1	0	0
T6	267	0	0	0
T7	2157	2	0	0
T8	223	0	0	0
T9	2684	0	0	0
T10	551	0	0	0
T13	5100	0	0	0
T14	489	0	0	0
T16	0	4	0	0
T17	0	10	0	0
T28	0	2	0	0
T32	345	0	0	0
T33	411	1	0	0
T36	0	2	0	0
T39	0	1	0	0
T117	0	1	0	0
T118	0	1	0	0

UsbClkPwrDown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3497557	9705	0	0
T1	202	1	0	0
T2	426	0	0	0
T3	740	0	0	0
T4	824	4	0	0
T5	159	0	0	0
T6	267	0	0	0
T7	2157	10	0	0
T8	223	0	0	0
T9	2684	6	0	0
T10	551	1	0	0
T34	0	9	0	0
T35	0	1	0	0
T36	0	7	0	0
T99	0	4	0	0
T118	0	3	0	0

UsbClkPwrUp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3497557	120921	0	0
T1	202	9	0	0
T2	426	0	0	0
T3	740	0	0	0
T4	824	28	0	0
T5	159	0	0	0
T6	267	0	0	0
T7	2157	80	0	0
T8	223	0	0	0
T9	2684	104	0	0
T10	551	13	0	0
T33	0	35	0	0
T34	0	73	0	0
T35	0	10	0	0
T36	0	88	0	0
T99	0	37	0	0