Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	17149627	14851	0	0
intr_enable_rd_A	17149627	34117	0	0
reset_en_rd_A	17149627	1527	0	0
reset_en_regwen_rd_A	17149627	1413	0	0
wake_info_capture_dis_rd_A	17149627	1327	0	0
wakeup_en_rd_A	17149627	1951	0	0
wakeup_en_regwen_rd_A	17149627	1223	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17149627	14851	0	0
T23	25850	27	0	0
T24	81221	23	0	0
T25	0	14	0	0
T43	4219	0	0	0
T45	1759	0	0	0
T46	11638	0	0	0
T50	0	113	0	0
T51	0	162	0	0
T53	0	23	0	0
T54	0	48	0	0
T55	0	27	0	0
T60	21415	0	0	0
T61	1024	0	0	0
T62	1848	0	0	0
T63	2327	0	0	0
T64	3673	0	0	0
T67	0	4	0	0
T119	0	3	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17149627	34117	0	0
T2	2947	25	0	0
T3	1700	0	0	0
T4	8026	0	0	0
T5	2030	12	0	0
T6	853	0	0	0
T7	20080	0	0	0
T8	1351	0	0	0
T9	4517	0	0	0
T10	1772	0	0	0
T13	25313	0	0	0
T15	0	25	0	0
T16	0	33	0	0
T28	0	109	0	0
T34	0	39	0	0
T35	0	1	0	0
T37	0	67	0	0
T39	0	10	0	0
T118	0	50	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17149627	1527	0	0
T23	25850	11	0	0
T24	81221	11	0	0
T25	0	25	0	0
T43	4219	0	0	0
T45	1759	0	0	0
T46	11638	0	0	0
T55	0	30	0	0
T60	21415	0	0	0
T61	1024	0	0	0
T62	1848	0	0	0
T63	2327	0	0	0
T64	3673	0	0	0
T67	0	9	0	0
T119	0	9	0	0
T120	0	6	0	0
T121	0	47	0	0
T122	0	20	0	0
T123	0	41	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17149627	1413	0	0
T23	25850	6	0	0
T24	81221	12	0	0
T25	0	26	0	0
T43	4219	0	0	0
T45	1759	0	0	0
T46	11638	0	0	0
T55	0	35	0	0
T60	21415	0	0	0
T61	1024	0	0	0
T62	1848	0	0	0
T63	2327	0	0	0
T64	3673	0	0	0
T67	0	4	0	0
T119	0	2	0	0
T120	0	13	0	0
T121	0	42	0	0
T122	0	14	0	0
T123	0	31	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17149627	1327	0	0
T23	25850	12	0	0
T24	81221	26	0	0
T25	0	10	0	0
T43	4219	0	0	0
T45	1759	0	0	0
T46	11638	0	0	0
T55	0	39	0	0
T60	21415	0	0	0
T61	1024	0	0	0
T62	1848	0	0	0
T63	2327	0	0	0
T64	3673	0	0	0
T67	0	13	0	0
T119	0	7	0	0
T120	0	18	0	0
T121	0	30	0	0
T122	0	26	0	0
T123	0	42	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17149627	1951	0	0
T23	25850	19	0	0
T24	81221	20	0	0
T25	0	15	0	0
T43	4219	0	0	0
T45	1759	0	0	0
T46	11638	0	0	0
T55	0	28	0	0
T60	21415	0	0	0
T61	1024	0	0	0
T62	1848	0	0	0
T63	2327	0	0	0
T64	3673	0	0	0
T67	0	7	0	0
T120	0	19	0	0
T121	0	40	0	0
T122	0	19	0	0
T123	0	29	0	0
T124	0	20	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17149627	1223	0	0
T23	25850	8	0	0
T24	81221	12	0	0
T25	0	11	0	0
T43	4219	0	0	0
T45	1759	0	0	0
T46	11638	0	0	0
T55	0	35	0	0
T60	21415	0	0	0
T61	1024	0	0	0
T62	1848	0	0	0
T63	2327	0	0	0
T64	3673	0	0	0
T67	0	7	0	0
T119	0	3	0	0
T120	0	16	0	0
T121	0	18	0	0
T122	0	16	0	0
T123	0	41	0	0