Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	49629339	99290	0	0
StatusRise_A	49629339	111656	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49629339	99290	0	0
T1	6654	6	0	0
T2	8841	27	0	0
T3	5100	5	0	0
T4	24078	24	0	0
T5	6090	11	0	0
T6	2559	3	0	0
T7	60240	51	0	0
T8	4053	0	0	0
T9	13551	46	0	0
T10	5316	8	0	0
T13	0	180	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49629339	111656	0	0
T1	6654	9	0	0
T2	8841	30	0	0
T3	5100	7	0	0
T4	24078	26	0	0
T5	6090	14	0	0
T6	2559	9	0	0
T7	60240	53	0	0
T8	4053	6	0	0
T9	13551	48	0	0
T10	5316	11	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	16543113	37020	0	0
StatusRise_A	16543113	41440	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16543113	37020	0	0
T1	2218	2	0	0
T2	2947	9	0	0
T3	1700	2	0	0
T4	8026	10	0	0
T5	2030	4	0	0
T6	853	1	0	0
T7	20080	20	0	0
T8	1351	0	0	0
T9	4517	19	0	0
T10	1772	3	0	0
T13	0	60	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16543113	41440	0	0
T1	2218	3	0	0
T2	2947	10	0	0
T3	1700	3	0	0
T4	8026	11	0	0
T5	2030	5	0	0
T6	853	3	0	0
T7	20080	21	0	0
T8	1351	2	0	0
T9	4517	20	0	0
T10	1772	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	16543113	37021	0	0
StatusRise_A	16543113	41443	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16543113	37021	0	0
T1	2218	2	0	0
T2	2947	9	0	0
T3	1700	2	0	0
T4	8026	10	0	0
T5	2030	4	0	0
T6	853	1	0	0
T7	20080	20	0	0
T8	1351	0	0	0
T9	4517	19	0	0
T10	1772	3	0	0
T13	0	60	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16543113	41443	0	0
T1	2218	3	0	0
T2	2947	10	0	0
T3	1700	3	0	0
T4	8026	11	0	0
T5	2030	5	0	0
T6	853	3	0	0
T7	20080	21	0	0
T8	1351	2	0	0
T9	4517	20	0	0
T10	1772	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	16543113	25249	0	0
StatusRise_A	16543113	28773	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16543113	25249	0	0
T1	2218	2	0	0
T2	2947	9	0	0
T3	1700	1	0	0
T4	8026	4	0	0
T5	2030	3	0	0
T6	853	1	0	0
T7	20080	11	0	0
T8	1351	0	0	0
T9	4517	8	0	0
T10	1772	2	0	0
T13	0	60	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16543113	28773	0	0
T1	2218	3	0	0
T2	2947	10	0	0
T3	1700	1	0	0
T4	8026	4	0	0
T5	2030	4	0	0
T6	853	3	0	0
T7	20080	11	0	0
T8	1351	2	0	0
T9	4517	8	0	0
T10	1772	3	0	0