Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

41                      
42         1/1            always_comb reset_or_disable = !rst_ni || disable_sva;
           Tests:       T1 T2 T3 
43         1/1            always_comb esc_reset_or_disable = !rst_esc_ni || disable_sva;
           Tests:       T1 T2 T3 
44         1/1            always_comb slow_reset_or_disable = !rst_slow_ni || disable_sva;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	16543696	10503	0	0
EscTimeoutStoppedByClReset_A	16543113	2260680	0	0
EscTimeoutTriggersReset_A	3497557	433	0	0
RomAllowActiveState_A	16543113	41022	0	0
RomAllowCheckGoodState_A	16543113	41072	0	0
RomBlockActiveState_A	16543113	29377	0	0
RomBlockCheckGoodState_A	16543113	354131	0	0
RomIntgChkDisFalse_A	16543113	16033491	0	0
RomIntgChkDisTrue_A	16543113	117599	0	0
RstreqChkEsctimeout_A	16543113	2964	0	0
RstreqChkFsmterm_A	16543113	160	0	0
RstreqChkGlbesc_A	16543113	2964	0	0
RstreqChkMainpd_A	16543113	709005	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16543696	10503	0	0
T11	10064	209	0	0
T12	603	4	0	0
T15	6592	0	0	0
T16	3160	0	0	0
T29	6144	0	0	0
T35	1450	0	0	0
T36	3576	0	0	0
T37	7755	0	0	0
T40	9465	61	0	0
T41	2051	0	0	0
T126	0	417	0	0
T127	0	62	0	0
T128	0	16	0	0
T129	0	494	0	0
T130	0	2	0	0
T131	0	83	0	0
T132	0	198	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16543113	2260680	0	0
T1	2218	35	0	0
T2	2947	325	0	0
T3	1700	185	0	0
T4	8026	1393	0	0
T5	2030	0	0	0
T6	853	23	0	0
T7	20080	3714	0	0
T8	1351	16	0	0
T9	4517	453	0	0
T10	1772	233	0	0
T13	0	5110	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3497557	433	0	0
T6	267	3	0	0
T7	2157	0	0	0
T8	223	0	0	0
T9	2684	0	0	0
T10	551	0	0	0
T11	0	5	0	0
T12	0	7	0	0
T13	5100	0	0	0
T14	489	0	0	0
T32	345	0	0	0
T33	411	0	0	0
T34	1569	0	0	0
T40	0	5	0	0
T126	0	5	0	0
T127	0	4	0	0
T128	0	9	0	0
T133	0	7	0	0
T134	0	4	0	0
T135	0	3	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16543113	41022	0	0
T1	2218	3	0	0
T2	2947	10	0	0
T3	1700	3	0	0
T4	8026	11	0	0
T5	2030	5	0	0
T6	853	3	0	0
T7	20080	21	0	0
T8	1351	2	0	0
T9	4517	20	0	0
T10	1772	4	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16543113	41072	0	0
T1	2218	3	0	0
T2	2947	10	0	0
T3	1700	3	0	0
T4	8026	11	0	0
T5	2030	5	0	0
T6	853	3	0	0
T7	20080	21	0	0
T8	1351	2	0	0
T9	4517	20	0	0
T10	1772	4	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16543113	29377	0	0
T12	603	0	0	0
T15	6591	1496	0	0
T16	3160	0	0	0
T18	4166	0	0	0
T27	1530	146	0	0
T29	6143	0	0	0
T37	7754	0	0	0
T40	9464	0	0	0
T41	2050	0	0	0
T46	0	10	0	0
T62	0	203	0	0
T99	6485	0	0	0
T136	0	14	0	0
T137	0	454	0	0
T138	0	594	0	0
T139	0	914	0	0
T140	0	10	0	0
T141	0	15	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16543113	354131	0	0
T4	8026	184	0	0
T5	2030	0	0	0
T6	853	0	0	0
T7	20080	0	0	0
T8	1351	0	0	0
T9	4517	252	0	0
T10	1772	0	0	0
T13	25313	0	0	0
T14	3268	0	0	0
T15	0	1033	0	0
T17	0	253	0	0
T27	0	46	0	0
T28	0	936	0	0
T32	1016	0	0	0
T39	0	160	0	0
T42	0	1285	0	0
T116	0	2487	0	0
T117	0	3981	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16543113	16033491	0	0
T1	2218	2150	0	0
T2	2947	2854	0	0
T3	1700	1611	0	0
T4	8026	7957	0	0
T5	2030	1956	0	0
T6	853	689	0	0
T7	20080	19995	0	0
T8	1351	1172	0	0
T9	4517	4439	0	0
T10	1772	1715	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16543113	117599	0	0
T12	603	0	0	0
T15	6591	2675	0	0
T16	3160	0	0	0
T18	4166	0	0	0
T27	1530	710	0	0
T28	0	97	0	0
T29	6143	0	0	0
T37	7754	0	0	0
T40	9464	0	0	0
T41	2050	0	0	0
T46	0	235	0	0
T62	0	926	0	0
T99	6485	0	0	0
T116	0	1057	0	0
T137	0	265	0	0
T138	0	374	0	0
T142	0	561	0	0
T143	0	203	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16543113	2964	0	0
T2	2947	6	0	0
T3	1700	0	0	0
T4	8026	0	0	0
T5	2030	0	0	0
T6	853	1	0	0
T7	20080	0	0	0
T8	1351	1	0	0
T9	4517	0	0	0
T10	1772	0	0	0
T11	0	2	0	0
T12	0	1	0	0
T13	25313	20	0	0
T15	0	5	0	0
T29	0	3	0	0
T37	0	9	0	0
T41	0	5	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16543113	160	0	0
T11	10064	0	0	0
T13	25313	40	0	0
T14	3268	0	0	0
T15	6591	0	0	0
T21	0	40	0	0
T22	0	20	0	0
T29	6143	0	0	0
T30	0	20	0	0
T31	0	40	0	0
T32	1016	0	0	0
T33	1714	0	0	0
T34	14394	0	0	0
T35	1450	0	0	0
T36	3575	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16543113	2964	0	0
T2	2947	6	0	0
T3	1700	0	0	0
T4	8026	0	0	0
T5	2030	0	0	0
T6	853	1	0	0
T7	20080	0	0	0
T8	1351	1	0	0
T9	4517	0	0	0
T10	1772	0	0	0
T11	0	2	0	0
T12	0	1	0	0
T13	25313	20	0	0
T15	0	5	0	0
T29	0	3	0	0
T37	0	9	0	0
T41	0	5	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16543113	709005	0	0
T2	2947	327	0	0
T3	1700	0	0	0
T4	8026	329	0	0
T5	2030	0	0	0
T6	853	0	0	0
T7	20080	0	0	0
T8	1351	0	0	0
T9	4517	202	0	0
T10	1772	0	0	0
T13	25313	0	0	0
T15	0	1921	0	0
T18	0	22	0	0
T27	0	96	0	0
T29	0	145	0	0
T32	0	12	0	0
T37	0	973	0	0
T38	0	86	0	0