Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	16805523	15796	0	0
intr_enable_rd_A	16805523	27022	0	0
reset_en_rd_A	16805523	2088	0	0
reset_en_regwen_rd_A	16805523	1826	0	0
wake_info_capture_dis_rd_A	16805523	1804	0	0
wakeup_en_rd_A	16805523	3096	0	0
wakeup_en_regwen_rd_A	16805523	1739	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16805523	15796	0	0
T19	1343	0	0	0
T24	194938	26	0	0
T25	0	128	0	0
T26	0	98	0	0
T59	0	57	0	0
T71	0	7	0	0
T75	0	182	0	0
T81	1375	0	0	0
T82	11807	0	0	0
T83	6732	0	0	0
T84	851	0	0	0
T85	4729	0	0	0
T86	9363	0	0	0
T87	6995	0	0	0
T88	2963	0	0	0
T89	0	16	0	0
T121	0	3	0	0
T122	0	41	0	0
T123	0	10	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16805523	27022	0	0
T2	5626	11	0	0
T3	3698	0	0	0
T4	4287	0	0	0
T5	8853	45	0	0
T6	1625	0	0	0
T7	13417	0	0	0
T8	4186	117	0	0
T9	18385	0	0	0
T10	2485	0	0	0
T13	1794	0	0	0
T14	0	26	0	0
T15	0	38	0	0
T28	0	190	0	0
T34	0	52	0	0
T52	0	36	0	0
T74	0	49	0	0
T124	0	7	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16805523	2088	0	0
T71	0	15	0	0
T91	0	14	0	0
T121	149123	7	0	0
T125	0	17	0	0
T126	0	13	0	0
T127	0	12	0	0
T128	0	12	0	0
T129	0	33	0	0
T130	0	25	0	0
T131	0	13	0	0
T132	865	0	0	0
T133	3973	0	0	0
T134	4467	0	0	0
T135	12547	0	0	0
T136	15768	0	0	0
T137	2244	0	0	0
T138	2712	0	0	0
T139	4243	0	0	0
T140	5150	0	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16805523	1826	0	0
T71	0	28	0	0
T91	0	29	0	0
T121	149123	7	0	0
T125	0	21	0	0
T126	0	18	0	0
T127	0	8	0	0
T128	0	10	0	0
T129	0	14	0	0
T130	0	21	0	0
T131	0	19	0	0
T132	865	0	0	0
T133	3973	0	0	0
T134	4467	0	0	0
T135	12547	0	0	0
T136	15768	0	0	0
T137	2244	0	0	0
T138	2712	0	0	0
T139	4243	0	0	0
T140	5150	0	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16805523	1804	0	0
T71	0	13	0	0
T91	0	18	0	0
T121	149123	18	0	0
T125	0	29	0	0
T126	0	31	0	0
T127	0	21	0	0
T128	0	15	0	0
T129	0	35	0	0
T130	0	20	0	0
T131	0	22	0	0
T132	865	0	0	0
T133	3973	0	0	0
T134	4467	0	0	0
T135	12547	0	0	0
T136	15768	0	0	0
T137	2244	0	0	0
T138	2712	0	0	0
T139	4243	0	0	0
T140	5150	0	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16805523	3096	0	0
T71	0	17	0	0
T91	0	29	0	0
T121	149123	11	0	0
T125	0	27	0	0
T126	0	15	0	0
T127	0	12	0	0
T128	0	14	0	0
T129	0	17	0	0
T130	0	30	0	0
T131	0	19	0	0
T132	865	0	0	0
T133	3973	0	0	0
T134	4467	0	0	0
T135	12547	0	0	0
T136	15768	0	0	0
T137	2244	0	0	0
T138	2712	0	0	0
T139	4243	0	0	0
T140	5150	0	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16805523	1739	0	0
T71	0	13	0	0
T91	0	10	0	0
T121	149123	15	0	0
T125	0	23	0	0
T126	0	10	0	0
T127	0	9	0	0
T128	0	13	0	0
T129	0	25	0	0
T130	0	11	0	0
T131	0	21	0	0
T132	865	0	0	0
T133	3973	0	0	0
T134	4467	0	0	0
T135	12547	0	0	0
T136	15768	0	0	0
T137	2244	0	0	0
T138	2712	0	0	0
T139	4243	0	0	0
T140	5150	0	0	0