Unified Coverage Report :: Module :: pwrmgr

Module : pwrmgr

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.70	100.00	83.87	99.60		100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_ip_pwrmgr_component_0.1/rtl/pwrmgr.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	96.70	100.00	83.87	99.60		100.00	100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.70	100.00	83.87	99.60		100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.80	98.23	96.58	99.62	96.00	96.37	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
clkmgr_pwrmgr_io_sva_if	100.00						100.00
clkmgr_pwrmgr_main_sva_if	100.00						100.00
clkmgr_pwrmgr_usb_sva_if	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
i_wake_info	100.00	100.00	100.00			100.00
intr_wakeup	93.75	100.00	75.00			100.00	100.00
pwrmgr_clock_enables_sva_if	100.00	100.00	100.00				100.00
pwrmgr_csr_assert	100.00						100.00
pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00
pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_cdc	100.00	100.00	100.00			100.00	100.00
u_esc_clk_buf	100.00	100.00
u_esc_rst_buf	100.00	100.00
u_esc_rx	98.21			98.21
u_esc_timeout	92.79	100.00	75.00			96.15	100.00
u_esc_timeout_sync	100.00	100.00				100.00
u_fsm	98.66	100.00	98.44		94.87	100.00	100.00
u_ndm_sync	100.00	100.00				100.00
u_prim_lc_sync_dft_en	100.00	100.00				100.00	100.00
u_prim_lc_sync_hw_debug_en	100.00	100.00				100.00	100.00
u_reg	97.23	96.01	97.63	100.00		92.53	100.00
u_slow_fsm	99.41	100.00	97.06		100.00	100.00	100.00
u_sw_req_buf	100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr

	Line No.	Total	Covered	Percent
TOTAL		47	47	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
ALWAYS	179	4	4	100.00
ALWAYS	214	4	4	100.00
CONT_ASSIGN	229	1	1	100.00
CONT_ASSIGN	230	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	233	1	1	100.00
CONT_ASSIGN	234	1	1	100.00
CONT_ASSIGN	247	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
ALWAYS	339	6	6	100.00
CONT_ASSIGN	348	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	359	1	1	100.00
CONT_ASSIGN	360	1	1	100.00
CONT_ASSIGN	374	1	1	100.00
CONT_ASSIGN	379	1	1	100.00
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	502	1	1	100.00
CONT_ASSIGN	506	1	1	100.00
CONT_ASSIGN	514	1	1	100.00
CONT_ASSIGN	514	1	1	100.00
CONT_ASSIGN	514	1	1	100.00
CONT_ASSIGN	514	1	1	100.00
CONT_ASSIGN	514	1	1	100.00
CONT_ASSIGN	514	1	1	100.00
CONT_ASSIGN	519	1	1	100.00
CONT_ASSIGN	519	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	580	1	1	100.00
CONT_ASSIGN	581	1	1	100.00
CONT_ASSIGN	654	1	1	100.00
CONT_ASSIGN	658	1	1	100.00
CONT_ASSIGN	715	0	0
ALWAYS	719	0	0

107                     
108        1/1            assign ndm_req_valid = ndmreset_req_q;
           Tests:       T1 T2 T3 
109                     
110                       ////////////////////////////
111                       ///  escalation detections
112                       ////////////////////////////
113                     
114                       logic clk_lc;
115                       logic rst_lc_n;
116        1/1            assign clk_lc = clk_lc_i;
           Tests:       T1 T2 T3 
117        1/1            assign rst_lc_n = rst_lc_ni;
           Tests:       T1 T2 T3 
118                     
119                       logic clk_esc;
120                       logic rst_esc_n;
121                       prim_clock_buf #(
122                         .NoFpgaBuf(1'b1)
123                       ) u_esc_clk_buf (
124                         .clk_i(clk_esc_i),
125                         .clk_o(clk_esc)
126                       );
127                     
128                       prim_clock_buf #(
129                         .NoFpgaBuf(1'b1)
130                       ) u_esc_rst_buf (
131                         .clk_i(rst_esc_ni),
132                         .clk_o(rst_esc_n)
133                       );
134                     
135                       logic esc_rst_req_d, esc_rst_req_q;
136                       prim_esc_receiver #(
137                         .N_ESC_SEV   (alert_handler_reg_pkg::N_ESC_SEV),
138                         .PING_CNT_DW (alert_handler_reg_pkg::PING_CNT_DW)
139                       ) u_esc_rx (
140                         .clk_i(clk_esc),
141                         .rst_ni(rst_esc_n),
142                         .esc_req_o(esc_rst_req_d),
143                         .esc_rx_o(esc_rst_rx_o),
144                         .esc_tx_i(esc_rst_tx_i)
145                       );
146                     
147                       // These assertions use formal or simulation to prove that once esc_rst_req is latched, we expect
148                       // to see the lc reset requests in pwr_rst_o. The one exception is when escalation requests are
149                       // cancelled while the CPU fetch is disabled, meaning the fast fsm is inactive.
150                     `ifdef SIMULATION
151                       // In simulation mode, the prim_cdc_rand_delay module inserts a random one cycle delay to the
152                       // two flop synchronizers. There are two CDCs in the path from escalation reset to the fast fsm
153                       // receiving it, one to the slow clock, and one back to the fast one. And there are additional
154                       // cycles in the fast fsm to generate outputs. However, esc_rst_req_q can be dropped due to
155                       // rst_lc_n, which will cause slow_peri_reqs_masked.rstreqs[ResetEscIdx] to drop.
156                       `ASSERT(PwrmgrSecCmEscToSlowResetReq_A,
157                               esc_rst_req_q |-> ##[1:5] !esc_rst_req_q || slow_peri_reqs_masked.rstreqs[ResetEscIdx],
158                               clk_slow_i, !rst_slow_ni)
159                       `ASSERT(PwrmgrSecCmFsmEscToResetReq_A,
160                               slow_peri_reqs_masked.rstreqs[ResetEscIdx] |->
161                               ##[1:4] !slow_peri_reqs_masked.rstreqs[ResetEscIdx] || u_fsm.reset_reqs_i[ResetEscIdx],
162                               clk_i, !rst_ni)
163                     `else
164                       `ASSERT(PwrmgrSecCmEscToSlowResetReq_A,
165                               esc_rst_req_d |-> ##[2:3] (
166                                   (!esc_rst_req_d && lc_ctrl_pkg::lc_tx_test_false_loose(fetch_en_o)) ||
167                                   slow_peri_reqs_masked.rstreqs[ResetEscIdx]
168                               ), clk_slow_i, !rst_slow_ni)
169                       `ASSERT(PwrmgrSlowResetReqToFsmResetReq_A,
170                               slow_peri_reqs_masked.rstreqs[ResetEscIdx] |-> ##1 u_fsm.reset_reqs_i[ResetEscIdx],
171                               clk_i, !rst_ni)
172                     `endif
173                     
174                       `ASSERT(PwrmgrSecCmEscToLCReset_A, u_fsm.reset_reqs_i[ResetEscIdx] &&
175                               u_fsm.state_q == FastPwrStateActive |-> ##4 pwr_rst_o.rst_lc_req == 2'b11,
176                               clk_i, !rst_ni)
177                     
178                       always_ff @(posedge clk_lc or negedge rst_lc_n) begin
179        1/1              if (!rst_lc_n) begin
           Tests:       T1 T2 T3 
180        1/1                esc_rst_req_q <= '0;
           Tests:       T1 T2 T3 
181        1/1              end else if (esc_rst_req_d) begin
           Tests:       T1 T2 T3 
182                           // once latched, do not clear until reset
183        1/1                esc_rst_req_q <= 1'b1;
           Tests:       T2 T13 T14 
184                         end
                        MISSING_ELSE
185                       end
186                     
187                       localparam int EscTimeOutCnt = 128;
188                       logic esc_timeout, esc_timeout_lc_d, esc_timeout_lc_q;
189                       // SEC_CM: ESC_RX.CLK.BKGN_CHK, ESC_RX.CLK.LOCAL_ESC
190                       prim_clock_timeout #(
191                         .TimeOutCnt(EscTimeOutCnt)
192                       ) u_esc_timeout (
193                         .clk_chk_i(clk_esc),
194                         .rst_chk_ni(rst_esc_n),
195                         .clk_i,
196                         .rst_ni,
197                         // if any ip clock enable is turned on, then the escalation
198                         // clocks are also enabled.
199                         .en_i(|pwr_clk_o),
200                         .timeout_o(esc_timeout)
201                       );
202                     
203                       prim_flop_2sync #(
204                         .Width(1),
205                         .ResetValue('0)
206                       ) u_esc_timeout_sync (
207                         .clk_i(clk_lc),
208                         .rst_ni(rst_lc_n),
209                         .d_i(esc_timeout),
210                         .q_o(esc_timeout_lc_d)
211                       );
212                     
213                       always_ff @(posedge clk_lc or negedge rst_lc_n) begin
214        1/1              if (!rst_lc_n) begin
           Tests:       T1 T2 T3 
215        1/1                esc_timeout_lc_q <= '0;
           Tests:       T1 T2 T3 
216        1/1              end else if (esc_timeout_lc_d) begin
           Tests:       T1 T2 T3 
217                           // once latched, do not clear until reset
218        1/1                esc_timeout_lc_q <= 1'b1;
           Tests:       T10 T11 T12 
219                         end
                        MISSING_ELSE
220                       end
221                     
222                     
223                       ////////////////////////////
224                       ///  async declarations
225                       ////////////////////////////
226                       pwr_peri_t peri_reqs_raw;
227                       logic slow_rst_req;
228                     
229        1/1            assign peri_reqs_raw.wakeups = wakeups_i;
           Tests:       T1 T3 T4 
230        1/1            assign peri_reqs_raw.rstreqs[NumRstReqs-1:0] = rstreqs_i;
           Tests:       T1 T2 T5 
231        1/1            assign peri_reqs_raw.rstreqs[ResetMainPwrIdx] = slow_rst_req;
           Tests:       T1 T2 T3 
232                       // SEC_CM: ESC_RX.CLK.LOCAL_ESC, CTRL_FLOW.GLOBAL_ESC
233        1/1            assign peri_reqs_raw.rstreqs[ResetEscIdx] = esc_rst_req_q | esc_timeout_lc_q;
           Tests:       T1 T2 T3 
234        1/1            assign peri_reqs_raw.rstreqs[ResetNdmIdx] = ndm_req_valid;
           Tests:       T1 T2 T3 
235                     
236                       ////////////////////////////
237                       ///  Software reset request
238                       ////////////////////////////
239                       logic sw_rst_req;
240                       prim_buf #(
241                         .Width(1)
242                       ) u_sw_req_buf (
243                         .in_i(prim_mubi_pkg::mubi4_test_true_strict(sw_rst_req_i)),
244                         .out_o(sw_rst_req)
245                       );
246                     
247        1/1            assign peri_reqs_raw.rstreqs[ResetSwReqIdx] = sw_rst_req;
           Tests:       T2 T8 T14 
248                     
249                       ////////////////////////////
250                       ///  clk_i domain declarations
251                       ////////////////////////////
252                     
253                       pwrmgr_reg2hw_t reg2hw;
254                       pwrmgr_hw2reg_t hw2reg;
255                       pwr_peri_t peri_reqs_masked;
256                     
257                       logic req_pwrup;
258                       logic ack_pwrup;
259                       logic req_pwrdn;
260                       logic ack_pwrdn;
261                       logic fsm_invalid;
262                       logic clr_slow_req;
263                       logic usb_ip_clk_en;
264                       logic usb_ip_clk_status;
265                       pwrup_cause_e pwrup_cause;
266                     
267                       logic low_power_fall_through;
268                       logic low_power_abort;
269                     
270                       pwr_flash_t flash_rsp;
271                       pwr_otp_rsp_t otp_rsp;
272                     
273                       prim_mubi_pkg::mubi4_t rom_ctrl_done;
274                       prim_mubi_pkg::mubi4_t rom_ctrl_good;
275                     
276                       logic core_sleeping;
277                       logic low_power_entry;
278                     
279                       ////////////////////////////
280                       ///  clk_slow_i domain declarations
281                       ////////////////////////////
282                     
283                       // Captured signals
284                       // These signals, though on clk_i domain, are safe for clk_slow_i to use
285                       logic [NumWkups-1:0] slow_wakeup_en;
286                       logic [NumRstReqs-1:0] slow_reset_en;
287                     
288                       pwr_ast_rsp_t slow_ast;
289                       pwr_peri_t slow_peri_reqs, slow_peri_reqs_masked;
290                     
291                       pwrup_cause_e slow_pwrup_cause;
292                       logic slow_pwrup_cause_toggle;
293                       logic slow_req_pwrup;
294                       logic slow_ack_pwrup;
295                       logic slow_req_pwrdn;
296                       logic slow_ack_pwrdn;
297                       logic slow_fsm_invalid;
298                       logic slow_main_pd_n;
299                       logic slow_io_clk_en;
300                       logic slow_core_clk_en;
301                       logic slow_usb_clk_en_lp;
302                       logic slow_usb_clk_en_active;
303                       logic slow_clr_req;
304                       logic slow_usb_ip_clk_en;
305                       logic slow_usb_ip_clk_status;
306                     
307                     
308                     
309                       ////////////////////////////
310                       ///  Register module
311                       ////////////////////////////
312                       logic [NumAlerts-1:0] alert_test, alerts;
313                       logic low_power_hint;
314                       logic lowpwr_cfg_wen;
315                       logic clr_hint;
316                       logic wkup;
317                       logic clr_cfg_lock;
318                       logic reg_intg_err;
319                     
320                       // SEC_CM: BUS.INTEGRITY
321                       // SEC_CM: CTRL.CONFIG.REGWEN, WAKEUP.CONFIG.REGWEN, RESET.CONFIG.REGWEN
322                       pwrmgr_reg_top u_reg (
323                         .clk_i,
324                         .rst_ni,
325                         .clk_lc_i  (clk_lc  ),
326                         .rst_lc_ni (rst_lc_n),
327                         .tl_i,
328                         .tl_o,
329                         .reg2hw,
330                         .hw2reg,
331                         .intg_err_o (reg_intg_err)
332                       );
333                     
334                       // whenever low power entry begins, wipe the hint
335                       assign hw2reg.control.low_power_hint.d = 1'b0;
336        1/1            assign hw2reg.control.low_power_hint.de = clr_hint;
           Tests:       T1 T2 T3 
337                     
338                       always_ff @(posedge clk_i or negedge rst_ni) begin
339        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
340        1/1                lowpwr_cfg_wen <= 1'b1;
           Tests:       T1 T2 T3 
341        1/1              end else if (!lowpwr_cfg_wen && (clr_cfg_lock || wkup)) begin
           Tests:       T1 T2 T3 
342        1/1                lowpwr_cfg_wen <= 1'b1;
           Tests:       T1 T3 T4 
343        1/1              end else if (low_power_entry) begin
           Tests:       T1 T2 T3 
344        1/1                lowpwr_cfg_wen <= 1'b0;
           Tests:       T1 T3 T4 
345                         end
                        MISSING_ELSE
346                       end
347                     
348        1/1            assign hw2reg.ctrl_cfg_regwen.d = lowpwr_cfg_wen;
           Tests:       T1 T2 T3 
349                     
350        1/1            assign hw2reg.fault_status.reg_intg_err.de    = reg_intg_err;
           Tests:       T1 T2 T3 
351                       assign hw2reg.fault_status.reg_intg_err.d     = 1'b1;
352        1/1            assign hw2reg.fault_status.esc_timeout.de     = esc_timeout_lc_q;
           Tests:       T1 T2 T3 
353                       assign hw2reg.fault_status.esc_timeout.d      = 1'b1;
354                     
355                       // The main power domain glitch automatically causes a reset, so regsitering
356                       // an alert is functionally pointless.  However, if an attacker somehow manages/
357                       // to silence the reset, this gives us one potential back-up path through alert_handler.
358                       // Allow capture of main_pd fault status whenever the system is live.
359        1/1            assign hw2reg.fault_status.main_pd_glitch.de  = pwr_clk_o.main_ip_clk_en;
           Tests:       T1 T2 T3 
360        1/1            assign hw2reg.fault_status.main_pd_glitch.d   = peri_reqs_masked.rstreqs[ResetMainPwrIdx] |
           Tests:       T1 T2 T3 
361                                                                       reg2hw.fault_status.main_pd_glitch.q;
362                     
363                       `ASSERT(GlitchStatusPersist_A, $rose(reg2hw.fault_status.main_pd_glitch.q) |->
364                               reg2hw.fault_status.main_pd_glitch.q until !rst_lc_ni)
365                     
366                       ////////////////////////////
367                       ///  alerts
368                       ////////////////////////////
369                     
370                       // the logic below assumes there is only one alert, so make an
371                       // explicit assertion check for it.
372                       `ASSERT_INIT(AlertNumCheck_A, NumAlerts == 1)
373                     
374        1/1            assign alert_test = {
           Tests:       T1 T2 T3 
375                         reg2hw.alert_test.q &
376                         reg2hw.alert_test.qe
377                       };
378                     
379        1/1            assign alerts[0] = reg2hw.fault_status.reg_intg_err.q |
           Tests:       T1 T2 T3 
380                                          reg2hw.fault_status.esc_timeout.q |
381                                          reg2hw.fault_status.main_pd_glitch.q;
382                     
383                       for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_tx
384                         prim_alert_sender #(
385                           .AsyncOn(AlertAsyncOn[i]),
386                           .IsFatal(1'b1)
387                         ) u_prim_alert_sender (
388                           .clk_i         ( clk_lc        ),
389                           .rst_ni        ( rst_lc_n      ),
390                           .alert_test_i  ( alert_test[i] ),
391                           .alert_req_i   ( alerts[i]     ),
392                           .alert_ack_o   (               ),
393                           .alert_state_o (               ),
394                           .alert_rx_i    ( alert_rx_i[i] ),
395                           .alert_tx_o    ( alert_tx_o[i] )
396                         );
397                       end
398                     
399                       ////////////////////////////
400                       ///  cdc handling
401                       ////////////////////////////
402                     
403                       pwrmgr_cdc u_cdc (
404                         .clk_i,
405                         .rst_ni,
406                         .clk_slow_i,
407                         .rst_slow_ni,
408                     
409                         // slow domain signals
410                         .slow_req_pwrup_i(slow_req_pwrup),
411                         .slow_ack_pwrdn_i(slow_ack_pwrdn),
412                         .slow_fsm_invalid_i(slow_fsm_invalid),
413                         .slow_pwrup_cause_toggle_i(slow_pwrup_cause_toggle),
414                         .slow_pwrup_cause_i(slow_pwrup_cause),
415                         .slow_wakeup_en_o(slow_wakeup_en),
416                         .slow_reset_en_o(slow_reset_en),
417                         .slow_main_pd_no(slow_main_pd_n),
418                         .slow_io_clk_en_o(slow_io_clk_en),
419                         .slow_core_clk_en_o(slow_core_clk_en),
420                         .slow_usb_clk_en_lp_o(slow_usb_clk_en_lp),
421                         .slow_usb_clk_en_active_o(slow_usb_clk_en_active),
422                         .slow_req_pwrdn_o(slow_req_pwrdn),
423                         .slow_ack_pwrup_o(slow_ack_pwrup),
424                         .slow_ast_o(slow_ast),
425                         .slow_peri_reqs_o(slow_peri_reqs),
426                         .slow_peri_reqs_masked_i(slow_peri_reqs_masked),
427                         .slow_clr_req_o(slow_clr_req),
428                         .slow_usb_ip_clk_en_i(slow_usb_ip_clk_en),
429                         .slow_usb_ip_clk_status_o(slow_usb_ip_clk_status),
430                     
431                         // fast domain signals
432                         .req_pwrdn_i(req_pwrdn),
433                         .ack_pwrup_i(ack_pwrup),
434                         .cfg_cdc_sync_i(reg2hw.cfg_cdc_sync.qe & reg2hw.cfg_cdc_sync.q),
435                         .cdc_sync_done_o(hw2reg.cfg_cdc_sync.de),
436                         .wakeup_en_i(reg2hw.wakeup_en),
437                         .reset_en_i(reg2hw.reset_en),
438                         .main_pd_ni(reg2hw.control.main_pd_n.q),
439                         .io_clk_en_i(reg2hw.control.io_clk_en.q),
440                         .core_clk_en_i(reg2hw.control.core_clk_en.q),
441                         .usb_clk_en_lp_i(reg2hw.control.usb_clk_en_lp.q),
442                         .usb_clk_en_active_i(reg2hw.control.usb_clk_en_active.q),
443                         .ack_pwrdn_o(ack_pwrdn),
444                         .fsm_invalid_o(fsm_invalid),
445                         .req_pwrup_o(req_pwrup),
446                         .pwrup_cause_o(pwrup_cause),
447                         .peri_reqs_o(peri_reqs_masked),
448                         .clr_slow_req_i(clr_slow_req),
449                         .usb_ip_clk_en_o(usb_ip_clk_en),
450                         .usb_ip_clk_status_i(usb_ip_clk_status),
451                     
452                         // AST signals
453                         .ast_i(pwr_ast_i),
454                     
455                         // peripheral signals
456                         .peri_i(peri_reqs_raw),
457                     
458                         // flash handshake
459                         .flash_i(pwr_flash_i),
460                         .flash_o(flash_rsp),
461                     
462                         // OTP signals
463                         .otp_i(pwr_otp_i),
464                         .otp_o(otp_rsp),
465                     
466                         // rom_ctrl signals
467                         .rom_ctrl_done_i(rom_ctrl_i.done),
468                         .rom_ctrl_done_o(rom_ctrl_done),
469                     
470                         // core sleeping
471                         .core_sleeping_i(pwr_cpu_i.core_sleeping),
472                         .core_sleeping_o(core_sleeping)
473                     
474                       );
475                       // rom_ctrl_i.good is not synchronized as it acts as a "payload" signal
476                       // to "done". Good is only observed if "done" is high.
477        1/1            assign rom_ctrl_good = rom_ctrl_i.good;
           Tests:       T5 T7 T9 
478                       assign hw2reg.cfg_cdc_sync.d = 1'b0;
479                     
480                       ////////////////////////////
481                       ///  Wakup and reset capture
482                       ////////////////////////////
483                     
484                       // reset and wakeup requests are captured into the slow clock domain and then
485                       // fanned out to other domains as necessary.  This ensures there is not a huge
486                       // time gap between when the slow clk domain sees the signal vs when the fast
487                       // clock domains see it.  This creates redundant syncing but keeps the time
488                       // scale approximately the same across all domains.
489                       //
490                       // This also implies that these signals must be at least 1 clk_slow pulse long
491                       //
492                       // Since resets are not latched inside pwrmgr, there exists a corner case where
493                       // non-always-on reset requests may get wiped out by a graceful low power entry
494                       // It's not clear if this is really an issue at the moment, but something to keep
495                       // in mind if future changes are needed.
496                       //
497                       // Latching the reset requests is not difficult, but the bigger question is who
498                       // should clear it and when that should happen. If the clearing does not work
499                       // correctly, it is possible for the device to end up in a permanent reset loop,
500                       // and that would be very undesirable.
501                     
502        1/1            assign slow_peri_reqs_masked.wakeups = slow_peri_reqs.wakeups & slow_wakeup_en;
           Tests:       T1 T2 T3 
503                       // msb is software request
504                       // the internal requests include escalation and internal requests
505                       // the lsbs are the software enabled peripheral requests.
506        1/1            assign slow_peri_reqs_masked.rstreqs = slow_peri_reqs.rstreqs &
           Tests:       T1 T2 T3 
507                                                              {{NumSwRstReq{1'b1}},
508                                                               {NumDebugRstReqs{1'b1}},
509                                                               {NumIntRstReqs{1'b1}},
510                                                               slow_reset_en};
511                     
512                       for (genvar i = 0; i < NumWkups; i++) begin : gen_wakeup_status
513                         assign hw2reg.wake_status[i].de = 1'b1;
514        6/6              assign hw2reg.wake_status[i].d  = peri_reqs_masked.wakeups[i];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
515                       end
516                     
517                       for (genvar i = 0; i < NumRstReqs; i++) begin : gen_reset_status
518                         assign hw2reg.reset_status[i].de = 1'b1;
519        2/2              assign hw2reg.reset_status[i].d  = peri_reqs_masked.rstreqs[i];
           Tests:       T1 T2 T3  | T1 T2 T3 
520                       end
521                     
522                       assign hw2reg.escalate_reset_status.de = 1'b1;
523        1/1            assign hw2reg.escalate_reset_status.d = peri_reqs_masked.rstreqs[NumRstReqs];
           Tests:       T1 T2 T3 
524                     
525                     
526                       ////////////////////////////
527                       ///  clk_slow FSM
528                       ////////////////////////////
529                     
530                       pwrmgr_slow_fsm u_slow_fsm (
531                         .clk_i                (clk_slow_i),
532                         .rst_ni               (rst_slow_ni),
533                         .rst_main_ni          (rst_main_ni),
534                         .wakeup_i             (|slow_peri_reqs_masked.wakeups),
535                         .reset_req_i          (|slow_peri_reqs_masked.rstreqs),
536                         .ast_i                (slow_ast),
537                         .req_pwrup_o          (slow_req_pwrup),
538                         .pwrup_cause_o        (slow_pwrup_cause),
539                         .pwrup_cause_toggle_o (slow_pwrup_cause_toggle),
540                         .ack_pwrup_i          (slow_ack_pwrup),
541                         .req_pwrdn_i          (slow_req_pwrdn),
542                         .ack_pwrdn_o          (slow_ack_pwrdn),
543                         .rst_req_o            (slow_rst_req),
544                         .fsm_invalid_o        (slow_fsm_invalid),
545                         .clr_req_i            (slow_clr_req),
546                         .usb_ip_clk_en_o      (slow_usb_ip_clk_en),
547                         .usb_ip_clk_status_i  (slow_usb_ip_clk_status),
548                     
549                         .main_pd_ni           (slow_main_pd_n),
550                         .io_clk_en_i          (slow_io_clk_en),
551                         .core_clk_en_i        (slow_core_clk_en),
552                         .usb_clk_en_lp_i      (slow_usb_clk_en_lp),
553                         .usb_clk_en_active_i  (slow_usb_clk_en_active),
554                     
555                         // outputs to AST - These are on the slow clock domain
556                         // TBD - need to check this with partners
557                         .ast_o                (pwr_ast_o)
558                       );
559                     
560                       lc_ctrl_pkg::lc_tx_t lc_dft_en;
561                       prim_lc_sync u_prim_lc_sync_dft_en (
562                         .clk_i,
563                         .rst_ni,
564                         .lc_en_i(lc_dft_en_i),
565                         .lc_en_o({lc_dft_en})
566                       );
567                     
568                       lc_ctrl_pkg::lc_tx_t lc_hw_debug_en;
569                       prim_lc_sync u_prim_lc_sync_hw_debug_en (
570                         .clk_i,
571                         .rst_ni,
572                         .lc_en_i(lc_hw_debug_en_i),
573                         .lc_en_o({lc_hw_debug_en})
574                       );
575                     
576                       ////////////////////////////
577                       ///  clk FSM
578                       ////////////////////////////
579                     
580        1/1            assign low_power_hint = reg2hw.control.low_power_hint.q == LowPower;
           Tests:       T1 T2 T3 
581        1/1            assign low_power_entry = core_sleeping & low_power_hint;
           Tests:       T1 T2 T3 
582                     
583                       pwrmgr_fsm u_fsm (
584                         .clk_i,
585                         .rst_ni,
586                         .clk_slow_i,
587                         .rst_slow_ni,
588                     
589                         // interface with slow_fsm
590                         .req_pwrup_i         (req_pwrup),
591                         .pwrup_cause_i       (pwrup_cause), // por, wake or reset request
592                         .ack_pwrup_o         (ack_pwrup),
593                         .req_pwrdn_o         (req_pwrdn),
594                         .ack_pwrdn_i         (ack_pwrdn),
595                         .low_power_entry_i   (low_power_entry),
596                         .reset_reqs_i        (peri_reqs_masked.rstreqs),
597                         .fsm_invalid_i       (fsm_invalid),
598                         .clr_slow_req_o      (clr_slow_req),
599                         .usb_ip_clk_en_i     (usb_ip_clk_en),
600                         .usb_ip_clk_status_o (usb_ip_clk_status),
601                     
602                         // cfg
603                         .main_pd_ni        (reg2hw.control.main_pd_n.q),
604                     
605                         // consumed in pwrmgr
606                         .wkup_o            (wkup),
607                         .clr_cfg_lock_o    (clr_cfg_lock),
608                         .fall_through_o    (low_power_fall_through),
609                         .abort_o           (low_power_abort),
610                         .clr_hint_o        (clr_hint),
611                     
612                         // rstmgr
613                         .pwr_rst_o         (pwr_rst_o),
614                         .pwr_rst_i         (pwr_rst_i),
615                     
616                         // clkmgr
617                         .ips_clk_en_o      (pwr_clk_o),
618                         .clk_en_status_i   (pwr_clk_i),
619                     
620                         // otp
621                         .otp_init_o        (pwr_otp_o.otp_init),
622                         .otp_done_i        (otp_rsp.otp_done),
623                         .otp_idle_i        (otp_rsp.otp_idle),
624                     
625                         // lc
626                         .lc_init_o         (pwr_lc_o.lc_init),
627                         .lc_done_i         (pwr_lc_i.lc_done),
628                         .lc_idle_i         (pwr_lc_i.lc_idle),
629                         .lc_dft_en_i       (lc_dft_en),
630                         .lc_hw_debug_en_i  (lc_hw_debug_en),
631                     
632                         // flash
633                         .flash_idle_i      (flash_rsp.flash_idle),
634                     
635                         // rom_ctrl
636                         .rom_ctrl_done_i   (rom_ctrl_done),
637                         .rom_ctrl_good_i   (rom_ctrl_good),
638                     
639                         // processing element
640                         .fetch_en_o,
641                     
642                         // pinmux and other peripherals
643                         .strap_o,
644                         .low_power_o
645                       );
646                     
647                       ////////////////////////////
648                       ///  Wakeup Info Capture
649                       ////////////////////////////
650                     
651                       logic wake_info_wen;
652                       logic [TotalWakeWidth-1:0] wake_info_data;
653                     
654        1/1            assign wake_info_wen = reg2hw.wake_info.abort.qe |
           Tests:       T1 T2 T3 
655                                              reg2hw.wake_info.fall_through.qe |
656                                              reg2hw.wake_info.reasons.qe;
657                     
658        1/1            assign wake_info_data = {reg2hw.wake_info.abort.q,
           Tests:       T1 T2 T3 
659                                                reg2hw.wake_info.fall_through.q,
660                                                reg2hw.wake_info.reasons.q};
661                     
662                       pwrmgr_wake_info i_wake_info (
663                         .clk_i,
664                         .rst_ni,
665                         .wr_i            (wake_info_wen),
666                         .data_i          (wake_info_data),
667                         .start_capture_i (low_power_o),
668                         .record_dis_i    (reg2hw.wake_info_capture_dis.q),
669                         .wakeups_i       (peri_reqs_masked.wakeups),
670                         .fall_through_i  (low_power_fall_through),
671                         .abort_i         (low_power_abort),
672                         .info_o          (hw2reg.wake_info)
673                       );
674                     
675                       ////////////////////////////
676                       ///  Interrupts
677                       ////////////////////////////
678                     
679                       // This interrupt is asserted whenever the fast FSM transitions
680                       // into active state.  However, it does not assert during POR
681                       prim_intr_hw #(.Width(1)) intr_wakeup (
682                         .clk_i,
683                         .rst_ni,
684                         .event_intr_i           (wkup),
685                         .reg2hw_intr_enable_q_i (reg2hw.intr_enable.q),
686                         .reg2hw_intr_test_q_i   (reg2hw.intr_test.q),
687                         .reg2hw_intr_test_qe_i  (reg2hw.intr_test.qe),
688                         .reg2hw_intr_state_q_i  (reg2hw.intr_state.q),
689                         .hw2reg_intr_state_de_o (hw2reg.intr_state.de),
690                         .hw2reg_intr_state_d_o  (hw2reg.intr_state.d),
691                         .intr_o                 (intr_wakeup_o)
692                       );
693                     
694                     
695                       ////////////////////////////
696                       ///  Assertions
697                       ////////////////////////////
698                     
699                       `ASSERT_KNOWN(TlDValidKnownO_A,  tl_o.d_valid     )
700                       `ASSERT_KNOWN(TlAReadyKnownO_A,  tl_o.a_ready     )
701                       `ASSERT_KNOWN(AlertsKnownO_A,    alert_tx_o       )
702                       `ASSERT_KNOWN(AstKnownO_A,       pwr_ast_o        )
703                       `ASSERT_KNOWN(RstKnownO_A,       pwr_rst_o        )
704                       `ASSERT_KNOWN(ClkKnownO_A,       pwr_clk_o        )
705                       `ASSERT_KNOWN(OtpKnownO_A,       pwr_otp_o        )
706                       `ASSERT_KNOWN(LcKnownO_A,        pwr_lc_o         )
707                       `ASSERT_KNOWN(IntrKnownO_A,      intr_wakeup_o    )
708                     
709                       // EscTimeOutCnt also sets the required clock ratios between escalator and local clock
710                       // Ie, clk_lc cannot be so slow that the timeout count is reached
711                       `ifdef INC_ASSERT
712                       //VCS coverage off
713                       // pragma coverage off
714                       logic effective_rst_n;
715        unreachable    assign effective_rst_n = clk_lc_i && rst_ni;
716                     
717                       logic [31:0] cnt;
718                       always_ff @(posedge clk_i or negedge effective_rst_n) begin
719        unreachable      if (!effective_rst_n) begin
720        unreachable        cnt <= '0;
721                         end else begin
722        unreachable        cnt <= cnt + 1'b1;

---

Cond Coverage for Module : pwrmgr

	Total	Covered	Percent
Conditions	31	26	83.87
Logical	31	26	83.87
Non-Logical	0	0
Event	0	0

 LINE       233
 EXPRESSION (esc_rst_req_q | esc_timeout_lc_q)
             ------1------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T13,T14

 LINE       341
 EXPRESSION (((!lowpwr_cfg_wen)) && (clr_cfg_lock || wkup))
             ---------1---------    -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       341
 SUB-EXPRESSION (clr_cfg_lock || wkup)
                 ------1-----    --2-

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T15,T16
1	0	Covered	T1,T2,T3

 LINE       360
 EXPRESSION (peri_reqs_masked.rstreqs[pwrmgr_reg_pkg::ResetMainPwrIdx] | reg2hw.fault_status.main_pd_glitch.q)
             ----------------------------1----------------------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T17,T18,T19
1	0	Covered	T2,T5,T7

 LINE       374
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       379
 EXPRESSION (reg2hw.fault_status.reg_intg_err.q | reg2hw.fault_status.esc_timeout.q | reg2hw.fault_status.main_pd_glitch.q)
             -----------------1----------------   ----------------2----------------   ------------------3-----------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T2,T5,T7
0	1	0	Covered	T10,T11,T12
1	0	0	Covered	T20,T21,T22

 LINE       403
 EXPRESSION (reg2hw.cfg_cdc_sync.qe & reg2hw.cfg_cdc_sync.q)
             -----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       580
 EXPRESSION (reg2hw.control.low_power_hint.q == LowPower)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       581
 EXPRESSION (core_sleeping & low_power_hint)
             ------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       654
 EXPRESSION (reg2hw.wake_info.abort.qe | reg2hw.wake_info.fall_through.qe | reg2hw.wake_info.reasons.qe)
             ------------1------------   ----------------2---------------   -------------3-------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

---

Toggle Coverage for Module : pwrmgr

	Total	Covered	Percent
Totals	80	79	98.75
Total Bits	506	504	99.60
Total Bits 0->1	253	252	99.60
Total Bits 1->0	253	252	99.60

Ports	80	79	98.75
Port Bits	506	504	99.60
Port Bits 0->1	253	252	99.60
Port Bits 1->0	253	252	99.60

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_slow_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_slow_ni	Yes	Yes	T2,T5,T10	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T5,T10	Yes	T1,T2,T3	INPUT
rst_main_ni	Yes	Yes	T2,T5,T7	Yes	T2,T5,T7	INPUT
clk_lc_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_lc_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_esc_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_esc_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T5	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T3,T10,T23	Yes	T3,T10,T23	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T2,T5,T7	Yes	T2,T5,T7	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T2,T5,T7	Yes	T2,T5,T7	OUTPUT
pwr_ast_i.main_pok	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
pwr_ast_i.usb_clk_val	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
pwr_ast_i.io_clk_val	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
pwr_ast_i.core_clk_val	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
pwr_ast_i.slow_clk_val	No	No		No		INPUT
pwr_ast_o.usb_clk_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwr_ast_o.io_clk_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwr_ast_o.core_clk_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwr_ast_o.slow_clk_en	Unreachable	Unreachable		Unreachable		OUTPUT
pwr_ast_o.pwr_clamp	Yes	Yes	T1,T2,T3	Yes	T2,T3,T4	OUTPUT
pwr_ast_o.pwr_clamp_env	Yes	Yes	T1,T2,T3	Yes	T2,T3,T4	OUTPUT
pwr_ast_o.main_pd_n	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
pwr_rst_i.rst_sys_src_n[1:0]	Yes	Yes	T1,T2,T5	Yes	T1,T2,T3	INPUT
pwr_rst_i.rst_lc_src_n[1:0]	Yes	Yes	T1,T2,T5	Yes	T1,T2,T3	INPUT
pwr_rst_o.reset_cause[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwr_rst_o.rstreqs[4:0]	Yes	Yes	T1,T2,T5	Yes	T1,T2,T5	OUTPUT
pwr_rst_o.rst_sys_req[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T5	OUTPUT
pwr_rst_o.rst_lc_req[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T5	OUTPUT
pwr_clk_o.usb_ip_clk_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwr_clk_o.io_ip_clk_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwr_clk_o.main_ip_clk_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwr_clk_i.usb_status	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
pwr_clk_i.io_status	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
pwr_clk_i.main_status	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
pwr_otp_i.otp_idle	Yes	Yes	T6,T15,T16	Yes	T1,T3,T4	INPUT
pwr_otp_i.otp_done	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
pwr_otp_o.otp_init	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwr_lc_i.lc_idle	Yes	Yes	T6,T15,T16	Yes	T1,T3,T4	INPUT
pwr_lc_i.lc_done	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
pwr_lc_o.lc_init	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwr_flash_i.flash_idle	Yes	Yes	T6,T15,T16	Yes	T1,T3,T4	INPUT
pwr_cpu_i.core_sleeping	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
fetch_en_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
lc_hw_debug_en_i[3:0]	Yes	Yes	T7,T14,T27	Yes	T7,T14,T27	INPUT
lc_dft_en_i[3:0]	Yes	Yes	T7,T14,T28	Yes	T7,T14,T27	INPUT
wakeups_i[5:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
rstreqs_i[1:0]	Yes	Yes	T1,T2,T5	Yes	T1,T2,T5	INPUT
ndmreset_req_i	Yes	Yes	T2,T14,T29	Yes	T2,T14,T29	INPUT
strap_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
low_power_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
rom_ctrl_i.good[3:0]	Yes	Yes	T5,T7,T9	Yes	T5,T7,T9	INPUT
rom_ctrl_i.done[3:0]	Yes	Yes	T5,T7,T9	Yes	T5,T7,T9	INPUT
sw_rst_req_i[3:0]	Yes	Yes	T2,T8,T14	Yes	T2,T8,T14	INPUT
esc_rst_tx_i.esc_n	Yes	Yes	T2,T13,T14	Yes	T2,T13,T14	INPUT
esc_rst_tx_i.esc_p	Yes	Yes	T2,T13,T14	Yes	T2,T13,T14	INPUT
esc_rst_rx_o.resp_n	Yes	Yes	T2,T13,T14	Yes	T2,T13,T14	OUTPUT
esc_rst_rx_o.resp_p	Yes	Yes	T2,T13,T14	Yes	T2,T13,T14	OUTPUT
intr_wakeup_o	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : pwrmgr

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
IF	179	3	3	100.00
IF	214	3	3	100.00
IF	339	4	4	100.00

179            if (!rst_lc_n) begin
               -1-  
180              esc_rst_req_q <= '0;
                 ==>
181            end else if (esc_rst_req_d) begin
                        -2-  
182              // once latched, do not clear until reset
183              esc_rst_req_q <= 1'b1;
                 ==>
184            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T13,T14
0	0	Covered	T1,T2,T3

214            if (!rst_lc_n) begin
               -1-  
215              esc_timeout_lc_q <= '0;
                 ==>
216            end else if (esc_timeout_lc_d) begin
                        -2-  
217              // once latched, do not clear until reset
218              esc_timeout_lc_q <= 1'b1;
                 ==>
219            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
0	0	Covered	T1,T2,T3

339            if (!rst_ni) begin
               -1-  
340              lowpwr_cfg_wen <= 1'b1;
                 ==>
341            end else if (!lowpwr_cfg_wen && (clr_cfg_lock || wkup)) begin
                        -2-  
342              lowpwr_cfg_wen <= 1'b1;
                 ==>
343            end else if (low_power_entry) begin
                        -3-  
344              lowpwr_cfg_wen <= 1'b0;
                 ==>
345            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	18	18	100.00	18	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	18	18	100.00	18	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertNumCheck_A	911	911	0	0
AlertsKnownO_A	16192248	15780773	0	0
AstKnownO_A	16192248	15780773	0	0
ClkKnownO_A	16192248	15780773	0	0
ClkRatio_A	16192248	15780773	0	0
FpvSecCmFsmCheck_A	16192248	80	0	0
FpvSecCmRegWeOnehotCheck_A	16192248	80	0	0
FpvSecCmSlowFsmCheck_A	3745713	80	0	0
GlitchStatusPersist_A	16192248	4500	0	0
IntrKnownO_A	16192248	15780773	0	0
LcKnownO_A	16192248	15780773	0	0
OtpKnownO_A	16192248	15780773	0	0
PwrmgrSecCmEscToLCReset_A	16192248	1553	0	0
PwrmgrSecCmEscToSlowResetReq_A	3745713	11951	0	0
PwrmgrSecCmFsmEscToResetReq_A	16192248	77526	0	0
RstKnownO_A	16192248	15780773	0	0
TlAReadyKnownO_A	16192248	15780773	0	0
TlDValidKnownO_A	16192248	15780773	0	0

AlertNumCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	911	911	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

AlertsKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16192248	15780773	0	0
T1	1427	1346	0	0
T2	5626	5477	0	0
T3	3698	3621	0	0
T4	4287	4195	0	0
T5	8853	8690	0	0
T6	1625	1539	0	0
T7	13417	13363	0	0
T8	4186	4090	0	0
T9	18385	18318	0	0
T10	2485	2318	0	0

AstKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16192248	15780773	0	0
T1	1427	1346	0	0
T2	5626	5477	0	0
T3	3698	3621	0	0
T4	4287	4195	0	0
T5	8853	8690	0	0
T6	1625	1539	0	0
T7	13417	13363	0	0
T8	4186	4090	0	0
T9	18385	18318	0	0
T10	2485	2318	0	0

ClkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16192248	15780773	0	0
T1	1427	1346	0	0
T2	5626	5477	0	0
T3	3698	3621	0	0
T4	4287	4195	0	0
T5	8853	8690	0	0
T6	1625	1539	0	0
T7	13417	13363	0	0
T8	4186	4090	0	0
T9	18385	18318	0	0
T10	2485	2318	0	0

ClkRatio_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16192248	15780773	0	0
T1	1427	1346	0	0
T2	5626	5477	0	0
T3	3698	3621	0	0
T4	4287	4195	0	0
T5	8853	8690	0	0
T6	1625	1539	0	0
T7	13417	13363	0	0
T8	4186	4090	0	0
T9	18385	18318	0	0
T10	2485	2318	0	0

FpvSecCmFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16192248	80	0	0
T12	1956	0	0	0
T15	2349	0	0	0
T20	15273	10	0	0
T21	0	20	0	0
T22	0	20	0	0
T30	0	20	0	0
T31	0	10	0	0
T32	1406	0	0	0
T33	6790	0	0	0
T34	7555	0	0	0
T35	6774	0	0	0
T36	8448	0	0	0
T37	4181	0	0	0
T38	2408	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16192248	80	0	0
T12	1956	0	0	0
T15	2349	0	0	0
T20	15273	10	0	0
T21	0	20	0	0
T22	0	20	0	0
T30	0	20	0	0
T31	0	10	0	0
T32	1406	0	0	0
T33	6790	0	0	0
T34	7555	0	0	0
T35	6774	0	0	0
T36	8448	0	0	0
T37	4181	0	0	0
T38	2408	0	0	0

FpvSecCmSlowFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3745713	80	0	0
T12	211	0	0	0
T15	672	0	0	0
T20	6996	10	0	0
T21	0	20	0	0
T22	0	20	0	0
T30	0	20	0	0
T31	0	10	0	0
T32	433	0	0	0
T33	526	0	0	0
T34	2846	0	0	0
T35	2365	0	0	0
T36	2038	0	0	0
T37	632	0	0	0
T38	242	0	0	0

GlitchStatusPersist_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16192248	4500	0	0
T2	5626	5	0	0
T3	3698	0	0	0
T4	4287	0	0	0
T5	8853	3	0	0
T6	1625	0	0	0
T7	13417	19	0	0
T8	4186	0	0	0
T9	18385	17	0	0
T10	2485	0	0	0
T13	1794	0	0	0
T14	0	1	0	0
T27	0	2	0	0
T29	0	2	0	0
T33	0	8	0	0
T35	0	4	0	0
T39	0	11	0	0

IntrKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16192248	15780773	0	0
T1	1427	1346	0	0
T2	5626	5477	0	0
T3	3698	3621	0	0
T4	4287	4195	0	0
T5	8853	8690	0	0
T6	1625	1539	0	0
T7	13417	13363	0	0
T8	4186	4090	0	0
T9	18385	18318	0	0
T10	2485	2318	0	0

LcKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16192248	15780773	0	0
T1	1427	1346	0	0
T2	5626	5477	0	0
T3	3698	3621	0	0
T4	4287	4195	0	0
T5	8853	8690	0	0
T6	1625	1539	0	0
T7	13417	13363	0	0
T8	4186	4090	0	0
T9	18385	18318	0	0
T10	2485	2318	0	0

OtpKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16192248	15780773	0	0
T1	1427	1346	0	0
T2	5626	5477	0	0
T3	3698	3621	0	0
T4	4287	4195	0	0
T5	8853	8690	0	0
T6	1625	1539	0	0
T7	13417	13363	0	0
T8	4186	4090	0	0
T9	18385	18318	0	0
T10	2485	2318	0	0

PwrmgrSecCmEscToLCReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16192248	1553	0	0
T2	5626	3	0	0
T3	3698	0	0	0
T4	4287	0	0	0
T5	8853	0	0	0
T6	1625	0	0	0
T7	13417	0	0	0
T8	4186	0	0	0
T9	18385	0	0	0
T10	2485	1	0	0
T11	0	6	0	0
T12	0	1	0	0
T13	1794	0	0	0
T14	0	1	0	0
T20	0	10	0	0
T27	0	1	0	0
T29	0	4	0	0
T33	0	3	0	0
T40	0	2	0	0

PwrmgrSecCmEscToSlowResetReq_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3745713	11951	0	0
T2	441	18	0	0
T3	683	0	0	0
T4	2595	0	0	0
T5	1530	0	0	0
T6	245	0	0	0
T7	20980	0	0	0
T8	1238	0	0	0
T9	11160	0	0	0
T10	205	0	0	0
T13	349	2	0	0
T14	0	5	0	0
T20	0	61	0	0
T21	0	51	0	0
T27	0	11	0	0
T29	0	20	0	0
T33	0	16	0	0
T41	0	23	0	0
T42	0	41	0	0

PwrmgrSecCmFsmEscToResetReq_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16192248	77526	0	0
T2	5626	163	0	0
T3	3698	0	0	0
T4	4287	0	0	0
T5	8853	0	0	0
T6	1625	0	0	0
T7	13417	0	0	0
T8	4186	0	0	0
T9	18385	0	0	0
T10	2485	43	0	0
T11	0	480	0	0
T12	0	22	0	0
T13	1794	9	0	0
T14	0	69	0	0
T20	0	151	0	0
T29	0	64	0	0
T33	0	208	0	0
T38	0	6	0	0

RstKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16192248	15780773	0	0
T1	1427	1346	0	0
T2	5626	5477	0	0
T3	3698	3621	0	0
T4	4287	4195	0	0
T5	8853	8690	0	0
T6	1625	1539	0	0
T7	13417	13363	0	0
T8	4186	4090	0	0
T9	18385	18318	0	0
T10	2485	2318	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16192248	15780773	0	0
T1	1427	1346	0	0
T2	5626	5477	0	0
T3	3698	3621	0	0
T4	4287	4195	0	0
T5	8853	8690	0	0
T6	1625	1539	0	0
T7	13417	13363	0	0
T8	4186	4090	0	0
T9	18385	18318	0	0
T10	2485	2318	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16192248	15780773	0	0
T1	1427	1346	0	0
T2	5626	5477	0	0
T3	3698	3621	0	0
T4	4287	4195	0	0
T5	8853	8690	0	0
T6	1625	1539	0	0
T7	13417	13363	0	0
T8	4186	4090	0	0
T9	18385	18318	0	0
T10	2485	2318	0	0