Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	48576744	105168	0	0
StatusRise_A	48576744	118217	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48576744	105168	0	0
T1	4281	6	0	0
T2	16878	42	0	0
T3	11094	17	0	0
T4	12861	42	0	0
T5	26559	48	0	0
T6	4875	35	0	0
T7	40251	229	0	0
T8	12558	12	0	0
T9	55155	224	0	0
T10	7455	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48576744	118217	0	0
T1	4281	9	0	0
T2	16878	48	0	0
T3	11094	19	0	0
T4	12861	44	0	0
T5	26559	53	0	0
T6	4875	38	0	0
T7	40251	231	0	0
T8	12558	15	0	0
T9	55155	226	0	0
T10	7455	9	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	16192248	39018	0	0
StatusRise_A	16192248	43684	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16192248	39018	0	0
T1	1427	2	0	0
T2	5626	14	0	0
T3	3698	6	0	0
T4	4287	18	0	0
T5	8853	19	0	0
T6	1625	12	0	0
T7	13417	90	0	0
T8	4186	4	0	0
T9	18385	91	0	0
T10	2485	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16192248	43684	0	0
T1	1427	3	0	0
T2	5626	16	0	0
T3	3698	7	0	0
T4	4287	19	0	0
T5	8853	21	0	0
T6	1625	13	0	0
T7	13417	91	0	0
T8	4186	5	0	0
T9	18385	92	0	0
T10	2485	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	16192248	39019	0	0
StatusRise_A	16192248	43685	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16192248	39019	0	0
T1	1427	2	0	0
T2	5626	14	0	0
T3	3698	6	0	0
T4	4287	18	0	0
T5	8853	19	0	0
T6	1625	12	0	0
T7	13417	90	0	0
T8	4186	4	0	0
T9	18385	91	0	0
T10	2485	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16192248	43685	0	0
T1	1427	3	0	0
T2	5626	16	0	0
T3	3698	7	0	0
T4	4287	19	0	0
T5	8853	21	0	0
T6	1625	13	0	0
T7	13417	91	0	0
T8	4186	5	0	0
T9	18385	92	0	0
T10	2485	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	16192248	27131	0	0
StatusRise_A	16192248	30848	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16192248	27131	0	0
T1	1427	2	0	0
T2	5626	14	0	0
T3	3698	5	0	0
T4	4287	6	0	0
T5	8853	10	0	0
T6	1625	11	0	0
T7	13417	49	0	0
T8	4186	4	0	0
T9	18385	42	0	0
T10	2485	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16192248	30848	0	0
T1	1427	3	0	0
T2	5626	16	0	0
T3	3698	5	0	0
T4	4287	6	0	0
T5	8853	11	0	0
T6	1625	12	0	0
T7	13417	49	0	0
T8	4186	5	0	0
T9	18385	42	0	0
T10	2485	3	0	0