Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

41                      
42         1/1            always_comb reset_or_disable = !rst_ni || disable_sva;
           Tests:       T1 T2 T3 
43         1/1            always_comb esc_reset_or_disable = !rst_esc_ni || disable_sva;
           Tests:       T1 T2 T3 
44         1/1            always_comb slow_reset_or_disable = !rst_slow_ni || disable_sva;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	16192808	10526	0	0
EscTimeoutStoppedByClReset_A	16192248	2215148	0	0
EscTimeoutTriggersReset_A	3745713	394	0	0
RomAllowActiveState_A	16192248	43263	0	0
RomAllowCheckGoodState_A	16192248	43316	0	0
RomBlockActiveState_A	16192248	25140	0	0
RomBlockCheckGoodState_A	16192248	327745	0	0
RomIntgChkDisFalse_A	16192248	15649416	0	0
RomIntgChkDisTrue_A	16192248	131357	0	0
RstreqChkEsctimeout_A	16192248	3469	0	0
RstreqChkFsmterm_A	16192248	160	0	0
RstreqChkGlbesc_A	16192248	3469	0	0
RstreqChkMainpd_A	16192248	668608	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16192808	10526	0	0
T10	2486	39	0	0
T11	10625	419	0	0
T12	0	28	0	0
T13	1794	0	0	0
T14	5240	0	0	0
T20	15274	0	0	0
T23	1576	0	0	0
T29	2935	0	0	0
T32	1407	0	0	0
T40	0	25	0	0
T43	3204	0	0	0
T52	4944	0	0	0
T81	0	5	0	0
T86	0	66	0	0
T141	0	11	0	0
T142	0	223	0	0
T143	0	375	0	0
T144	0	416	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16192248	2215148	0	0
T1	1427	14	0	0
T2	5626	559	0	0
T3	3698	424	0	0
T4	4287	678	0	0
T5	8853	791	0	0
T6	1625	0	0	0
T7	13417	1350	0	0
T8	4186	48	0	0
T9	18385	2286	0	0
T10	2485	13	0	0
T13	0	28	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3745713	394	0	0
T10	205	3	0	0
T11	152	5	0	0
T12	0	3	0	0
T13	349	0	0	0
T14	403	0	0	0
T20	6996	0	0	0
T23	285	0	0	0
T29	1064	0	0	0
T32	433	0	0	0
T40	0	6	0	0
T43	318	0	0	0
T52	2001	0	0	0
T81	0	3	0	0
T86	0	6	0	0
T141	0	2	0	0
T142	0	6	0	0
T143	0	5	0	0
T145	0	3	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16192248	43263	0	0
T1	1427	3	0	0
T2	5626	16	0	0
T3	3698	7	0	0
T4	4287	19	0	0
T5	8853	21	0	0
T6	1625	13	0	0
T7	13417	91	0	0
T8	4186	5	0	0
T9	18385	92	0	0
T10	2485	3	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16192248	43316	0	0
T1	1427	3	0	0
T2	5626	16	0	0
T3	3698	7	0	0
T4	4287	19	0	0
T5	8853	21	0	0
T6	1625	13	0	0
T7	13417	91	0	0
T8	4186	5	0	0
T9	18385	92	0	0
T10	2485	3	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16192248	25140	0	0
T9	18385	9	0	0
T10	2485	0	0	0
T11	10624	0	0	0
T13	1794	0	0	0
T14	5239	1414	0	0
T20	15273	0	0	0
T23	1576	0	0	0
T27	0	150	0	0
T29	2934	0	0	0
T43	3204	0	0	0
T52	4944	0	0	0
T85	0	522	0	0
T146	0	15	0	0
T147	0	303	0	0
T148	0	92	0	0
T149	0	822	0	0
T150	0	9	0	0
T151	0	627	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16192248	327745	0	0
T5	8853	251	0	0
T6	1625	0	0	0
T7	13417	593	0	0
T8	4186	0	0	0
T9	18385	900	0	0
T10	2485	0	0	0
T11	10624	0	0	0
T13	1794	0	0	0
T14	0	859	0	0
T16	0	896	0	0
T23	1576	0	0	0
T27	0	8	0	0
T28	0	2215	0	0
T35	0	322	0	0
T39	0	2222	0	0
T45	0	115	0	0
T52	4944	0	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16192248	15649416	0	0
T1	1427	1346	0	0
T2	5626	5477	0	0
T3	3698	3621	0	0
T4	4287	4195	0	0
T5	8853	8690	0	0
T6	1625	1539	0	0
T7	13417	13257	0	0
T8	4186	4090	0	0
T9	18385	18318	0	0
T10	2485	2318	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16192248	131357	0	0
T7	13417	106	0	0
T8	4186	0	0	0
T9	18385	0	0	0
T10	2485	0	0	0
T11	10624	0	0	0
T13	1794	0	0	0
T14	5239	1918	0	0
T23	1576	0	0	0
T28	0	1239	0	0
T29	2934	0	0	0
T52	4944	0	0	0
T82	0	232	0	0
T85	0	478	0	0
T147	0	318	0	0
T148	0	550	0	0
T149	0	1897	0	0
T152	0	2442	0	0
T153	0	531	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16192248	3469	0	0
T2	5626	5	0	0
T3	3698	0	0	0
T4	4287	0	0	0
T5	8853	0	0	0
T6	1625	0	0	0
T7	13417	0	0	0
T8	4186	0	0	0
T9	18385	0	0	0
T10	2485	1	0	0
T11	0	2	0	0
T12	0	1	0	0
T13	1794	4	0	0
T14	0	2	0	0
T20	0	10	0	0
T29	0	5	0	0
T33	0	7	0	0
T38	0	3	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16192248	160	0	0
T12	1956	0	0	0
T15	2349	0	0	0
T20	15273	20	0	0
T21	0	40	0	0
T22	0	40	0	0
T30	0	40	0	0
T31	0	20	0	0
T32	1406	0	0	0
T33	6790	0	0	0
T34	7555	0	0	0
T35	6774	0	0	0
T36	8448	0	0	0
T37	4181	0	0	0
T38	2408	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16192248	3469	0	0
T2	5626	5	0	0
T3	3698	0	0	0
T4	4287	0	0	0
T5	8853	0	0	0
T6	1625	0	0	0
T7	13417	0	0	0
T8	4186	0	0	0
T9	18385	0	0	0
T10	2485	1	0	0
T11	0	2	0	0
T12	0	1	0	0
T13	1794	4	0	0
T14	0	2	0	0
T20	0	10	0	0
T29	0	5	0	0
T33	0	7	0	0
T38	0	3	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16192248	668608	0	0
T2	5626	617	0	0
T3	3698	0	0	0
T4	4287	0	0	0
T5	8853	699	0	0
T6	1625	0	0	0
T7	13417	1129	0	0
T8	4186	0	0	0
T9	18385	1658	0	0
T10	2485	0	0	0
T13	1794	0	0	0
T14	0	659	0	0
T17	0	10	0	0
T23	0	11	0	0
T29	0	192	0	0
T33	0	933	0	0
T35	0	566	0	0