Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	389814	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

155192

1

T1

13

T2

25

T3

14

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	287487	1			T1	27		T2	97		T3	32
values[0x0]	128733	1			T1	5		T2	32		T3	19
values[0x1]	128786	1			T1	5		T2	30		T3	10

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	308881	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

236125

1

T1

18

T2

62

T3

22

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2029	1			T10	7		T23	1		T14	6
valid_sources[0x01]	1664	1			T10	4		T20	1		T34	1
valid_sources[0x02]	2983	1			T10	5		T14	6		T24	18
valid_sources[0x03]	1655	1			T6	4		T10	7		T34	2
valid_sources[0x04]	1786	1			T3	2		T6	1		T10	1
valid_sources[0x05]	2113	1			T3	2		T6	1		T9	7
valid_sources[0x06]	1644	1			T6	2		T9	15		T10	2
valid_sources[0x07]	1905	1			T1	3		T3	1		T5	2
valid_sources[0x08]	1714	1			T4	3		T6	1		T10	2
valid_sources[0x09]	2170	1			T10	3		T23	1		T36	1
valid_sources[0x0a]	2419	1			T5	1		T6	1		T10	3
valid_sources[0x0b]	1838	1			T6	2		T10	2		T14	1
valid_sources[0x0c]	2522	1			T10	3		T28	1		T57	1
valid_sources[0x0d]	2272	1			T6	2		T9	7		T10	3
valid_sources[0x0e]	1491	1			T6	1		T10	4		T14	13
valid_sources[0x0f]	2853	1			T10	5		T34	2		T36	1
valid_sources[0x10]	1807	1			T9	1		T10	5		T36	3
valid_sources[0x11]	1821	1			T6	1		T10	6		T23	11
valid_sources[0x12]	1759	1			T3	5		T10	2		T14	1
valid_sources[0x13]	3430	1			T10	7		T23	2		T14	3
valid_sources[0x14]	1624	1			T10	2		T14	1		T28	1
valid_sources[0x15]	1637	1			T10	3		T14	7		T28	1
valid_sources[0x16]	1620	1			T6	1		T9	6		T10	2
valid_sources[0x17]	2070	1			T6	1		T10	1		T14	3
valid_sources[0x18]	1897	1			T5	9		T9	1		T10	4
valid_sources[0x19]	1891	1			T3	2		T4	3		T10	4
valid_sources[0x1a]	1967	1			T6	1		T9	5		T10	3
valid_sources[0x1b]	2499	1			T6	1		T9	5		T10	1
valid_sources[0x1c]	1718	1			T5	4		T6	3		T10	3
valid_sources[0x1d]	1793	1			T4	3		T10	7		T34	1
valid_sources[0x1e]	1675	1			T10	1		T14	6		T15	1
valid_sources[0x1f]	3128	1			T6	2		T10	4		T14	4
valid_sources[0x20]	1821	1			T10	4		T14	17		T32	2
valid_sources[0x21]	1885	1			T6	1		T10	6		T14	6
valid_sources[0x22]	1735	1			T9	7		T10	5		T34	1
valid_sources[0x23]	1820	1			T6	3		T10	8		T23	2
valid_sources[0x24]	1606	1			T10	7		T23	1		T14	2
valid_sources[0x25]	1829	1			T3	1		T6	1		T10	6
valid_sources[0x26]	1940	1			T10	2		T23	3		T14	3
valid_sources[0x27]	2526	1			T10	3		T14	5		T13	2
valid_sources[0x28]	2158	1			T10	2		T14	2		T41	1
valid_sources[0x29]	2190	1			T6	2		T10	1		T14	11
valid_sources[0x2a]	1872	1			T1	1		T5	1		T6	1
valid_sources[0x2b]	2010	1			T10	3		T14	4		T15	1
valid_sources[0x2c]	2230	1			T10	4		T34	1		T15	1
valid_sources[0x2d]	1596	1			T10	3		T14	1		T15	2
valid_sources[0x2e]	1755	1			T4	1		T6	1		T10	2
valid_sources[0x2f]	1846	1			T4	3		T10	5		T14	4
valid_sources[0x30]	1596	1			T10	2		T14	1		T15	2
valid_sources[0x31]	1694	1			T10	5		T23	9		T14	1
valid_sources[0x32]	1547	1			T5	3		T6	1		T10	4
valid_sources[0x33]	2392	1			T10	3		T11	1		T14	2
valid_sources[0x34]	3443	1			T10	6		T15	2		T138	5
valid_sources[0x35]	1807	1			T5	7		T10	5		T23	3
valid_sources[0x36]	3223	1			T6	1		T10	4		T14	3
valid_sources[0x37]	4064	1			T1	1		T5	3		T10	1
valid_sources[0x38]	2440	1			T3	3		T6	1		T8	1
valid_sources[0x39]	1912	1			T9	5		T10	2		T14	2
valid_sources[0x3a]	3647	1			T6	1		T10	4		T14	7
valid_sources[0x3b]	2004	1			T6	1		T10	6		T28	1
valid_sources[0x3c]	2044	1			T6	1		T10	4		T14	1
valid_sources[0x3d]	1622	1			T1	1		T3	2		T6	3
valid_sources[0x3e]	1659	1			T3	1		T10	3		T14	2
valid_sources[0x3f]	1620	1			T3	1		T10	6		T14	7
valid_sources[0x40]	2908	1			T6	1		T9	9		T10	3
valid_sources[0x41]	1644	1			T14	2		T34	1		T27	1
valid_sources[0x42]	1704	1			T4	6		T6	1		T14	2
valid_sources[0x43]	2297	1			T3	1		T10	6		T14	2
valid_sources[0x44]	1589	1			T5	5		T6	1		T9	48
valid_sources[0x45]	1793	1			T10	4		T23	10		T14	7
valid_sources[0x46]	1826	1			T6	1		T10	3		T23	6
valid_sources[0x47]	2055	1			T10	2		T14	1		T13	1
valid_sources[0x48]	2596	1			T6	1		T7	1		T10	3
valid_sources[0x49]	1949	1			T6	2		T10	4		T13	2
valid_sources[0x4a]	1634	1			T6	2		T10	3		T28	3
valid_sources[0x4b]	1660	1			T6	4		T10	4		T23	1
valid_sources[0x4c]	1666	1			T6	2		T10	1		T14	5
valid_sources[0x4d]	1514	1			T10	1		T14	3		T28	1
valid_sources[0x4e]	1934	1			T6	1		T36	1		T57	1
valid_sources[0x4f]	2587	1			T6	1		T10	3		T28	2
valid_sources[0x50]	2722	1			T4	4		T10	5		T14	4
valid_sources[0x51]	3243	1			T10	2		T14	1		T34	2
valid_sources[0x52]	2011	1			T6	1		T10	1		T14	1
valid_sources[0x53]	4022	1			T1	2		T3	2		T9	6
valid_sources[0x54]	1856	1			T6	3		T10	6		T13	1
valid_sources[0x55]	1657	1			T10	1		T23	5		T14	13
valid_sources[0x56]	2387	1			T9	1		T10	4		T14	6
valid_sources[0x57]	2581	1			T6	1		T10	6		T23	14
valid_sources[0x58]	1631	1			T5	11		T6	1		T10	1
valid_sources[0x59]	1953	1			T1	1		T4	7		T10	5
valid_sources[0x5a]	1782	1			T6	1		T10	3		T23	2
valid_sources[0x5b]	2617	1			T6	2		T10	3		T36	2
valid_sources[0x5c]	2904	1			T10	4		T14	2		T36	2
valid_sources[0x5d]	1784	1			T4	4		T5	1		T6	2
valid_sources[0x5e]	1769	1			T4	9		T6	1		T9	6
valid_sources[0x5f]	2006	1			T6	1		T10	1		T14	7
valid_sources[0x60]	2798	1			T4	1		T10	1		T14	6
valid_sources[0x61]	2471	1			T6	1		T10	7		T23	1
valid_sources[0x62]	1907	1			T10	1		T23	2		T34	1
valid_sources[0x63]	1908	1			T6	1		T10	5		T14	1
valid_sources[0x64]	2027	1			T10	5		T14	1		T32	1
valid_sources[0x65]	2000	1			T10	6		T34	1		T15	1
valid_sources[0x66]	1762	1			T10	3		T32	1		T15	1
valid_sources[0x67]	3323	1			T5	2		T10	2		T14	1
valid_sources[0x68]	1679	1			T10	2		T34	1		T15	1
valid_sources[0x69]	3146	1			T3	2		T5	3		T23	13
valid_sources[0x6a]	2715	1			T5	4		T6	1		T10	2
valid_sources[0x6b]	1896	1			T10	7		T20	1		T36	1
valid_sources[0x6c]	1672	1			T3	1		T4	3		T10	3
valid_sources[0x6d]	2042	1			T1	1		T6	2		T10	1
valid_sources[0x6e]	1880	1			T10	5		T34	1		T36	3
valid_sources[0x6f]	1648	1			T4	3		T6	1		T10	2
valid_sources[0x70]	1875	1			T5	1		T10	3		T14	3
valid_sources[0x71]	1673	1			T10	1		T28	1		T32	1
valid_sources[0x72]	1731	1			T6	1		T9	2		T10	1
valid_sources[0x73]	4057	1			T6	2		T10	3		T23	2
valid_sources[0x74]	1866	1			T6	1		T10	3		T14	6
valid_sources[0x75]	2061	1			T1	1		T3	1		T4	2
valid_sources[0x76]	4328	1			T6	1		T10	3		T14	11
valid_sources[0x77]	1955	1			T10	7		T14	2		T13	5
valid_sources[0x78]	1655	1			T3	6		T6	3		T10	11
valid_sources[0x79]	3244	1			T6	1		T10	3		T41	1
valid_sources[0x7a]	2223	1			T3	1		T5	9		T10	4
valid_sources[0x7b]	1932	1			T6	1		T10	4		T14	6
valid_sources[0x7c]	1736	1			T6	2		T10	2		T14	4
valid_sources[0x7d]	1762	1			T6	2		T10	4		T23	4
valid_sources[0x7e]	2399	1			T10	3		T14	10		T41	1
valid_sources[0x7f]	1720	1			T6	2		T10	4		T32	1
valid_sources[0x80]	2078	1			T9	10		T10	5		T14	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

79628

1

T1

9

T2

12

T3

6

values[0x0]

all_enables

biggest_size

48648

1

T1

2

T2

11

T3

6

values[0x1]

all_enables

biggest_size

26916

1

T1

2

T2

2

T3

2