SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34007 | 1 | T10 | 314 | T14 | 381 | T27 | 314 | ||||
others[1] | 33925 | 1 | T10 | 326 | T14 | 402 | T27 | 268 | ||||
others[2] | 33754 | 1 | T10 | 285 | T14 | 426 | T27 | 294 | ||||
others[3] | 57054 | 1 | T10 | 487 | T14 | 665 | T27 | 524 | ||||
false | 15190 | 1 | T3 | 6 | T10 | 50 | T14 | 50 | ||||
true | 23848 | 1 | T1 | 1 | T2 | 1 | T3 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34132 | 1 | T10 | 258 | T14 | 426 | T27 | 293 | ||||
others[1] | 33926 | 1 | T10 | 327 | T14 | 402 | T27 | 307 | ||||
others[2] | 33887 | 1 | T10 | 312 | T14 | 374 | T13 | 2 | ||||
others[3] | 56692 | 1 | T10 | 502 | T14 | 675 | T27 | 495 | ||||
false | 10146 | 1 | T3 | 3 | T10 | 50 | T14 | 50 | ||||
true | 18848 | 1 | T1 | 1 | T2 | 1 | T3 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 569 | 1 | T2 | 1 | T9 | 10 | T28 | 1 | ||||
others[1] | 568 | 1 | T2 | 1 | T9 | 4 | T13 | 1 | ||||
others[2] | 608 | 1 | T9 | 4 | T28 | 1 | T36 | 4 | ||||
others[3] | 967 | 1 | T2 | 2 | T9 | 7 | T28 | 1 | ||||
false | 10683 | 1 | T1 | 1 | T2 | 14 | T3 | 1 | ||||
true | 2899 | 1 | T2 | 9 | T9 | 1 | T13 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |