Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	18331882	14765	0	0
intr_enable_rd_A	18331882	29464	0	0
reset_en_rd_A	18331882	1580	0	0
reset_en_regwen_rd_A	18331882	1539	0	0
wake_info_capture_dis_rd_A	18331882	1638	0	0
wakeup_en_rd_A	18331882	1978	0	0
wakeup_en_regwen_rd_A	18331882	1576	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18331882	14765	0	0
T18	2854	0	0	0
T24	50440	21	0	0
T25	0	6	0	0
T26	0	13	0	0
T37	9431	0	0	0
T38	1687	0	0	0
T39	3364	0	0	0
T40	3471	0	0	0
T43	2095	0	0	0
T48	0	60	0	0
T49	0	14	0	0
T76	0	58	0	0
T90	0	51	0	0
T134	0	139	0	0
T135	0	74	0	0
T136	0	17	0	0
T137	2121	0	0	0
T138	57675	0	0	0
T139	2111	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18331882	29464	0	0
T2	6865	36	0	0
T3	2729	0	0	0
T4	3161	29	0	0
T5	2627	0	0	0
T6	4175	0	0	0
T7	1005	0	0	0
T8	2050	0	0	0
T9	2032	0	0	0
T10	22973	0	0	0
T13	0	6	0	0
T23	9295	0	0	0
T27	0	175	0	0
T57	0	47	0	0
T58	0	33	0	0
T74	0	7	0	0
T130	0	125	0	0
T140	0	93	0	0
T141	0	27	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18331882	1580	0	0
T26	162569	26	0	0
T49	0	16	0	0
T50	0	16	0	0
T90	0	36	0	0
T91	0	34	0	0
T98	12618	0	0	0
T99	2081	0	0	0
T100	25212	0	0	0
T101	2927	0	0	0
T102	33331	0	0	0
T103	1297	0	0	0
T104	6861	0	0	0
T142	0	6	0	0
T143	0	15	0	0
T144	0	16	0	0
T145	0	9	0	0
T146	0	18	0	0
T147	2557	0	0	0
T148	5419	0	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18331882	1539	0	0
T26	162569	15	0	0
T49	0	24	0	0
T50	0	6	0	0
T90	0	23	0	0
T91	0	30	0	0
T98	12618	0	0	0
T99	2081	0	0	0
T100	25212	0	0	0
T101	2927	0	0	0
T102	33331	0	0	0
T103	1297	0	0	0
T104	6861	0	0	0
T142	0	12	0	0
T143	0	12	0	0
T144	0	22	0	0
T145	0	6	0	0
T146	0	29	0	0
T147	2557	0	0	0
T148	5419	0	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18331882	1638	0	0
T26	162569	25	0	0
T49	0	20	0	0
T50	0	8	0	0
T90	0	41	0	0
T91	0	14	0	0
T98	12618	0	0	0
T99	2081	0	0	0
T100	25212	0	0	0
T101	2927	0	0	0
T102	33331	0	0	0
T103	1297	0	0	0
T104	6861	0	0	0
T142	0	10	0	0
T143	0	6	0	0
T144	0	24	0	0
T145	0	7	0	0
T146	0	36	0	0
T147	2557	0	0	0
T148	5419	0	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18331882	1978	0	0
T26	162569	16	0	0
T49	0	16	0	0
T50	0	6	0	0
T90	0	10	0	0
T91	0	18	0	0
T98	12618	0	0	0
T99	2081	0	0	0
T100	25212	0	0	0
T101	2927	0	0	0
T102	33331	0	0	0
T103	1297	0	0	0
T104	6861	0	0	0
T142	0	10	0	0
T143	0	10	0	0
T144	0	18	0	0
T145	0	15	0	0
T146	0	26	0	0
T147	2557	0	0	0
T148	5419	0	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18331882	1576	0	0
T26	162569	22	0	0
T49	0	28	0	0
T50	0	19	0	0
T90	0	18	0	0
T91	0	21	0	0
T98	12618	0	0	0
T99	2081	0	0	0
T100	25212	0	0	0
T101	2927	0	0	0
T102	33331	0	0	0
T103	1297	0	0	0
T104	6861	0	0	0
T142	0	10	0	0
T143	0	16	0	0
T144	0	14	0	0
T145	0	11	0	0
T146	0	35	0	0
T147	2557	0	0	0
T148	5419	0	0	0