Unified Coverage Report :: Module :: prim_lc_sync

Module : prim_lc_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_lc_sync_dft_en	100.00	100.00					100.00
tb.dut.u_prim_lc_sync_hw_debug_en	100.00	100.00					100.00

---

Module Instance : tb.dut.u_prim_lc_sync_dft_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_lc_sync_hw_debug_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

Line Coverage for Module : prim_lc_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

67                            always_ff @(posedge clk_i) begin
68         1/1                  lc_en_in_sva_q <= lc_en_i;
           Tests:       T1 T2 T3 
69                            end
70                          `ASSERT(OutputDelay_A,
71                                  rst_ni |-> ##3 lc_en_o == {NumCopies{$past(lc_en_in_sva_q, 2)}} ||
72                                                 ($past(lc_en_in_sva_q, 2) != $past(lc_en_in_sva_q, 1)))
73                      `endif
74                        end else begin : gen_no_flops
75                          //VCS coverage off
76                          // pragma coverage off
77                      
78                          // This unused companion logic helps remove lint errors
79                          // for modules where clock and reset are used for assertions only
80                          // or nothing at all.
81                          // This logic will be removed for sythesis since it is unloaded.
82                          lc_ctrl_pkg::lc_tx_t unused_logic;
83                          always_ff @(posedge clk_i or negedge rst_ni) begin
84                            if (!rst_ni) begin
85                               unused_logic <= lc_ctrl_pkg::Off;
86                            end else begin
87                               unused_logic <= lc_en_i;
88                            end
89                          end
90                          //VCS coverage on
91                          // pragma coverage on
92                      
93                          assign lc_en = lc_en_i;
94                      
95                          `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96                        end
97                      
98                        for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99                          logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100                         for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101                           prim_sec_anchor_buf u_prim_buf (
102                             .in_i(lc_en[k]),
103                             .out_o(lc_en_out[k])
104                           );
105                         end
106        1/1              assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Module : prim_lc_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1880	1880	0	0
OutputsKnown_A	35633970	34785066	0	0
gen_flops.OutputDelay_A	35633970	34750026	0	5640

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1880	1880	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T7	2	2	0	0
T8	2	2	0	0
T9	2	2	0	0
T10	2	2	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35633970	34785066	0	0
T1	4932	4798	0	0
T2	13730	13624	0	0
T3	5458	5348	0	0
T4	6322	6138	0	0
T5	5254	5106	0	0
T6	8350	8198	0	0
T7	2010	1640	0	0
T8	4100	3188	0	0
T9	4064	3894	0	0
T10	45946	45704	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35633970	34750026	0	5640
T1	4932	4792	0	6
T2	13730	13618	0	6
T3	5458	5342	0	6
T4	6322	6132	0	6
T5	5254	5100	0	6
T6	8350	8192	0	6
T7	2010	1628	0	6
T8	4100	3152	0	6
T9	4064	3888	0	6
T10	45946	45692	0	6

Line Coverage for Instance : tb.dut.u_prim_lc_sync_dft_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

67                            always_ff @(posedge clk_i) begin
68         1/1                  lc_en_in_sva_q <= lc_en_i;
           Tests:       T1 T2 T3 
69                            end
70                          `ASSERT(OutputDelay_A,
71                                  rst_ni |-> ##3 lc_en_o == {NumCopies{$past(lc_en_in_sva_q, 2)}} ||
72                                                 ($past(lc_en_in_sva_q, 2) != $past(lc_en_in_sva_q, 1)))
73                      `endif
74                        end else begin : gen_no_flops
75                          //VCS coverage off
76                          // pragma coverage off
77                      
78                          // This unused companion logic helps remove lint errors
79                          // for modules where clock and reset are used for assertions only
80                          // or nothing at all.
81                          // This logic will be removed for sythesis since it is unloaded.
82                          lc_ctrl_pkg::lc_tx_t unused_logic;
83                          always_ff @(posedge clk_i or negedge rst_ni) begin
84                            if (!rst_ni) begin
85                               unused_logic <= lc_ctrl_pkg::Off;
86                            end else begin
87                               unused_logic <= lc_en_i;
88                            end
89                          end
90                          //VCS coverage on
91                          // pragma coverage on
92                      
93                          assign lc_en = lc_en_i;
94                      
95                          `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96                        end
97                      
98                        for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99                          logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100                         for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101                           prim_sec_anchor_buf u_prim_buf (
102                             .in_i(lc_en[k]),
103                             .out_o(lc_en_out[k])
104                           );
105                         end
106        1/1              assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_prim_lc_sync_dft_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	940	940	0	0
OutputsKnown_A	17816985	17392533	0	0
gen_flops.OutputDelay_A	17816985	17375013	0	2820

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	940	940	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17816985	17392533	0	0
T1	2466	2399	0	0
T2	6865	6812	0	0
T3	2729	2674	0	0
T4	3161	3069	0	0
T5	2627	2553	0	0
T6	4175	4099	0	0
T7	1005	820	0	0
T8	2050	1594	0	0
T9	2032	1947	0	0
T10	22973	22852	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17816985	17375013	0	2820
T1	2466	2396	0	3
T2	6865	6809	0	3
T3	2729	2671	0	3
T4	3161	3066	0	3
T5	2627	2550	0	3
T6	4175	4096	0	3
T7	1005	814	0	3
T8	2050	1576	0	3
T9	2032	1944	0	3
T10	22973	22846	0	3

Line Coverage for Instance : tb.dut.u_prim_lc_sync_hw_debug_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

67                            always_ff @(posedge clk_i) begin
68         1/1                  lc_en_in_sva_q <= lc_en_i;
           Tests:       T1 T2 T3 
69                            end
70                          `ASSERT(OutputDelay_A,
71                                  rst_ni |-> ##3 lc_en_o == {NumCopies{$past(lc_en_in_sva_q, 2)}} ||
72                                                 ($past(lc_en_in_sva_q, 2) != $past(lc_en_in_sva_q, 1)))
73                      `endif
74                        end else begin : gen_no_flops
75                          //VCS coverage off
76                          // pragma coverage off
77                      
78                          // This unused companion logic helps remove lint errors
79                          // for modules where clock and reset are used for assertions only
80                          // or nothing at all.
81                          // This logic will be removed for sythesis since it is unloaded.
82                          lc_ctrl_pkg::lc_tx_t unused_logic;
83                          always_ff @(posedge clk_i or negedge rst_ni) begin
84                            if (!rst_ni) begin
85                               unused_logic <= lc_ctrl_pkg::Off;
86                            end else begin
87                               unused_logic <= lc_en_i;
88                            end
89                          end
90                          //VCS coverage on
91                          // pragma coverage on
92                      
93                          assign lc_en = lc_en_i;
94                      
95                          `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96                        end
97                      
98                        for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99                          logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100                         for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101                           prim_sec_anchor_buf u_prim_buf (
102                             .in_i(lc_en[k]),
103                             .out_o(lc_en_out[k])
104                           );
105                         end
106        1/1              assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_prim_lc_sync_hw_debug_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	940	940	0	0
OutputsKnown_A	17816985	17392533	0	0
gen_flops.OutputDelay_A	17816985	17375013	0	2820

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	940	940	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17816985	17392533	0	0
T1	2466	2399	0	0
T2	6865	6812	0	0
T3	2729	2674	0	0
T4	3161	3069	0	0
T5	2627	2553	0	0
T6	4175	4099	0	0
T7	1005	820	0	0
T8	2050	1594	0	0
T9	2032	1947	0	0
T10	22973	22852	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17816985	17375013	0	2820
T1	2466	2396	0	3
T2	6865	6809	0	3
T3	2729	2671	0	3
T4	3161	3066	0	3
T5	2627	2550	0	3
T6	4175	4096	0	3
T7	1005	814	0	3
T8	2050	1576	0	3
T9	2032	1944	0	3
T10	22973	22846	0	3