Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	53450955	109201	0	0
StatusRise_A	53450955	122745	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53450955	109201	0	0
T1	7398	6	0	0
T2	20595	66	0	0
T3	8187	12	0	0
T4	9483	26	0	0
T5	7881	21	0	0
T6	12525	32	0	0
T7	3015	3	0	0
T8	6150	0	0	0
T9	6096	3	0	0
T10	68919	226	0	0
T23	0	25	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53450955	122745	0	0
T1	7398	9	0	0
T2	20595	69	0	0
T3	8187	14	0	0
T4	9483	28	0	0
T5	7881	24	0	0
T6	12525	34	0	0
T7	3015	9	0	0
T8	6150	18	0	0
T9	6096	6	0	0
T10	68919	231	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	17816985	40638	0	0
StatusRise_A	17816985	45496	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17816985	40638	0	0
T1	2466	2	0	0
T2	6865	22	0	0
T3	2729	4	0	0
T4	3161	9	0	0
T5	2627	8	0	0
T6	4175	14	0	0
T7	1005	1	0	0
T8	2050	0	0	0
T9	2032	1	0	0
T10	22973	91	0	0
T23	0	10	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17816985	45496	0	0
T1	2466	3	0	0
T2	6865	23	0	0
T3	2729	5	0	0
T4	3161	10	0	0
T5	2627	9	0	0
T6	4175	15	0	0
T7	1005	3	0	0
T8	2050	6	0	0
T9	2032	2	0	0
T10	22973	93	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	17816985	40639	0	0
StatusRise_A	17816985	45496	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17816985	40639	0	0
T1	2466	2	0	0
T2	6865	22	0	0
T3	2729	4	0	0
T4	3161	9	0	0
T5	2627	8	0	0
T6	4175	14	0	0
T7	1005	1	0	0
T8	2050	0	0	0
T9	2032	1	0	0
T10	22973	91	0	0
T23	0	10	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17816985	45496	0	0
T1	2466	3	0	0
T2	6865	23	0	0
T3	2729	5	0	0
T4	3161	10	0	0
T5	2627	9	0	0
T6	4175	15	0	0
T7	1005	3	0	0
T8	2050	6	0	0
T9	2032	2	0	0
T10	22973	93	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	17816985	27924	0	0
StatusRise_A	17816985	31753	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17816985	27924	0	0
T1	2466	2	0	0
T2	6865	22	0	0
T3	2729	4	0	0
T4	3161	8	0	0
T5	2627	5	0	0
T6	4175	4	0	0
T7	1005	1	0	0
T8	2050	0	0	0
T9	2032	1	0	0
T10	22973	44	0	0
T23	0	5	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17816985	31753	0	0
T1	2466	3	0	0
T2	6865	23	0	0
T3	2729	4	0	0
T4	3161	8	0	0
T5	2627	6	0	0
T6	4175	4	0	0
T7	1005	3	0	0
T8	2050	6	0	0
T9	2032	2	0	0
T10	22973	45	0	0