Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

41                      
42         1/1            always_comb reset_or_disable = !rst_ni || disable_sva;
           Tests:       T1 T2 T3 
43         1/1            always_comb esc_reset_or_disable = !rst_esc_ni || disable_sva;
           Tests:       T1 T2 T3 
44         1/1            always_comb slow_reset_or_disable = !rst_slow_ni || disable_sva;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	17817590	11979	0	0
EscTimeoutStoppedByClReset_A	17816985	2488205	0	0
EscTimeoutTriggersReset_A	3681730	430	0	0
RomAllowActiveState_A	17816985	45038	0	0
RomAllowCheckGoodState_A	17816985	45090	0	0
RomBlockActiveState_A	17816985	28558	0	0
RomBlockCheckGoodState_A	17816985	374172	0	0
RomIntgChkDisFalse_A	17816985	17268778	0	0
RomIntgChkDisTrue_A	17816985	123755	0	0
RstreqChkEsctimeout_A	17816985	3278	0	0
RstreqChkFsmterm_A	17816985	140	0	0
RstreqChkGlbesc_A	17816985	3278	0	0
RstreqChkMainpd_A	17816985	755907	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17817590	11979	0	0
T7	1005	1	0	0
T8	2050	0	0	0
T9	2033	0	0	0
T10	22973	0	0	0
T11	10392	300	0	0
T13	2249	0	0	0
T14	17427	0	0	0
T17	3483	0	0	0
T23	9295	0	0	0
T37	0	87	0	0
T41	2860	0	0	0
T97	0	32	0	0
T149	0	26	0	0
T150	0	82	0	0
T151	0	371	0	0
T152	0	2	0	0
T153	0	113	0	0
T154	0	67	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17816985	2488205	0	0
T1	2466	13	0	0
T2	6865	760	0	0
T3	2729	576	0	0
T4	3161	219	0	0
T5	2627	0	0	0
T6	4175	1236	0	0
T7	1005	14	0	0
T8	2050	18	0	0
T9	2032	12	0	0
T10	22973	3229	0	0
T23	0	1770	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3681730	430	0	0
T7	250	4	0	0
T8	630	0	0	0
T9	563	0	0	0
T10	7650	0	0	0
T11	148	4	0	0
T12	0	2	0	0
T13	677	0	0	0
T14	7838	0	0	0
T17	332	0	0	0
T23	1036	0	0	0
T37	0	5	0	0
T41	294	0	0	0
T97	0	5	0	0
T149	0	2	0	0
T150	0	4	0	0
T151	0	5	0	0
T152	0	3	0	0
T155	0	3	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17816985	45038	0	0
T1	2466	3	0	0
T2	6865	23	0	0
T3	2729	5	0	0
T4	3161	10	0	0
T5	2627	9	0	0
T6	4175	15	0	0
T7	1005	3	0	0
T8	2050	6	0	0
T9	2032	2	0	0
T10	22973	93	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17816985	45090	0	0
T1	2466	3	0	0
T2	6865	23	0	0
T3	2729	5	0	0
T4	3161	10	0	0
T5	2627	9	0	0
T6	4175	15	0	0
T7	1005	3	0	0
T8	2050	6	0	0
T9	2032	2	0	0
T10	22973	93	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17816985	28558	0	0
T13	2248	75	0	0
T14	17427	41	0	0
T15	3182	0	0	0
T20	17087	0	0	0
T28	2908	0	0	0
T31	842	0	0	0
T32	1533	0	0	0
T33	1135	0	0	0
T34	3843	0	0	0
T38	0	378	0	0
T41	2859	0	0	0
T96	0	175	0	0
T100	0	15	0	0
T141	0	231	0	0
T156	0	11	0	0
T157	0	228	0	0
T158	0	375	0	0
T159	0	162	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17816985	374172	0	0
T3	2729	69	0	0
T4	3161	0	0	0
T5	2627	0	0	0
T6	4175	0	0	0
T7	1005	0	0	0
T8	2050	0	0	0
T9	2032	0	0	0
T10	22973	1457	0	0
T11	10392	0	0	0
T13	0	99	0	0
T14	0	1114	0	0
T16	0	598	0	0
T23	9295	0	0	0
T24	0	1511	0	0
T27	0	2292	0	0
T35	0	253	0	0
T38	0	71	0	0
T138	0	4013	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17816985	17268778	0	0
T1	2466	2399	0	0
T2	6865	6812	0	0
T3	2729	2674	0	0
T4	3161	3069	0	0
T5	2627	2553	0	0
T6	4175	4099	0	0
T7	1005	820	0	0
T8	2050	1594	0	0
T9	2032	1947	0	0
T10	22973	22076	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17816985	123755	0	0
T10	22973	776	0	0
T11	10392	0	0	0
T13	2248	83	0	0
T14	17427	0	0	0
T17	3483	0	0	0
T20	17087	0	0	0
T23	9295	0	0	0
T27	0	1064	0	0
T28	2908	0	0	0
T31	842	0	0	0
T38	0	105	0	0
T41	2859	0	0	0
T96	0	158	0	0
T100	0	611	0	0
T141	0	225	0	0
T156	0	508	0	0
T157	0	1205	0	0
T160	0	1403	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17816985	3278	0	0
T2	6865	8	0	0
T3	2729	0	0	0
T4	3161	0	0	0
T5	2627	0	0	0
T6	4175	0	0	0
T7	1005	1	0	0
T8	2050	5	0	0
T9	2032	0	0	0
T10	22973	0	0	0
T11	0	2	0	0
T12	0	1	0	0
T13	0	4	0	0
T16	0	9	0	0
T20	0	20	0	0
T23	9295	0	0	0
T24	0	9	0	0
T28	0	6	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17816985	140	0	0
T12	2507	0	0	0
T15	3182	0	0	0
T16	47851	0	0	0
T20	17087	40	0	0
T21	0	20	0	0
T22	0	40	0	0
T29	0	20	0	0
T30	0	20	0	0
T31	842	0	0	0
T32	1533	0	0	0
T33	1135	0	0	0
T34	3843	0	0	0
T35	5552	0	0	0
T36	5982	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17816985	3278	0	0
T2	6865	8	0	0
T3	2729	0	0	0
T4	3161	0	0	0
T5	2627	0	0	0
T6	4175	0	0	0
T7	1005	1	0	0
T8	2050	5	0	0
T9	2032	0	0	0
T10	22973	0	0	0
T11	0	2	0	0
T12	0	1	0	0
T13	0	4	0	0
T16	0	9	0	0
T20	0	20	0	0
T23	9295	0	0	0
T24	0	9	0	0
T28	0	6	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17816985	755907	0	0
T2	6865	781	0	0
T3	2729	0	0	0
T4	3161	0	0	0
T5	2627	0	0	0
T6	4175	0	0	0
T7	1005	0	0	0
T8	2050	0	0	0
T9	2032	0	0	0
T10	22973	2816	0	0
T13	0	113	0	0
T14	0	1329	0	0
T16	0	1193	0	0
T17	0	17	0	0
T23	9295	0	0	0
T27	0	2676	0	0
T28	0	75	0	0
T31	0	25	0	0
T35	0	540	0	0