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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.95 98.23 96.58 99.62 96.00 96.37 100.00 98.85


Total test records in report: 1105
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
T807 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_esc_clk_rst_malfunc.2052997553 Sep 11 05:43:42 AM UTC 24 Sep 11 05:43:44 AM UTC 24 28746869 ps
T808 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_disable_rom_integrity_check.976264238 Sep 11 05:43:24 AM UTC 24 Sep 11 05:43:26 AM UTC 24 66964041 ps
T809 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_reset.2105578122 Sep 11 05:43:24 AM UTC 24 Sep 11 05:43:26 AM UTC 24 49070770 ps
T810 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_smoke.509600482 Sep 11 05:43:24 AM UTC 24 Sep 11 05:43:26 AM UTC 24 29538742 ps
T811 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_reset_invalid.1485940041 Sep 11 05:43:24 AM UTC 24 Sep 11 05:43:26 AM UTC 24 162791416 ps
T812 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_disable_rom_integrity_check.3240178011 Sep 11 05:43:42 AM UTC 24 Sep 11 05:43:44 AM UTC 24 69137217 ps
T813 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_aborted_low_power.1130701114 Sep 11 05:43:24 AM UTC 24 Sep 11 05:43:26 AM UTC 24 19234496 ps
T814 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_lowpower_wakeup_race.1675493758 Sep 11 05:43:24 AM UTC 24 Sep 11 05:43:26 AM UTC 24 228554888 ps
T815 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_global_esc.1972007090 Sep 11 05:43:24 AM UTC 24 Sep 11 05:43:26 AM UTC 24 30785969 ps
T816 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_global_esc.192866070 Sep 11 05:43:42 AM UTC 24 Sep 11 05:43:44 AM UTC 24 40304373 ps
T817 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_wakeup.328043669 Sep 11 05:43:24 AM UTC 24 Sep 11 05:43:26 AM UTC 24 209769638 ps
T818 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_esc_clk_rst_malfunc.1285253709 Sep 11 05:43:24 AM UTC 24 Sep 11 05:43:26 AM UTC 24 29758152 ps
T819 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_glitch.3997903701 Sep 11 05:43:24 AM UTC 24 Sep 11 05:43:26 AM UTC 24 87438746 ps
T820 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_sec_cm_ctrl_config_regwen.1367726013 Sep 11 05:43:24 AM UTC 24 Sep 11 05:43:26 AM UTC 24 189174362 ps
T821 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_disable_rom_integrity_check.2896098817 Sep 11 05:43:24 AM UTC 24 Sep 11 05:43:26 AM UTC 24 86495548 ps
T822 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_sec_cm_rstmgr_intersig_mubi.2263666696 Sep 11 05:43:24 AM UTC 24 Sep 11 05:43:26 AM UTC 24 53332199 ps
T823 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_lowpower_invalid.116107401 Sep 11 05:43:24 AM UTC 24 Sep 11 05:43:26 AM UTC 24 85493309 ps
T824 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_reset.1644843134 Sep 11 05:43:24 AM UTC 24 Sep 11 05:43:26 AM UTC 24 66578275 ps
T825 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_escalation_timeout.985600464 Sep 11 05:43:24 AM UTC 24 Sep 11 05:43:26 AM UTC 24 110344268 ps
T826 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_wakeup_reset.2963188042 Sep 11 05:43:24 AM UTC 24 Sep 11 05:43:26 AM UTC 24 263765147 ps
T827 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_smoke.354078949 Sep 11 05:43:24 AM UTC 24 Sep 11 05:43:26 AM UTC 24 39030042 ps
T828 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_glitch.2680739442 Sep 11 05:43:42 AM UTC 24 Sep 11 05:43:44 AM UTC 24 78284461 ps
T829 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_reset_invalid.2434167595 Sep 11 05:43:24 AM UTC 24 Sep 11 05:43:26 AM UTC 24 116825130 ps
T830 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_esc_clk_rst_malfunc.3503476932 Sep 11 05:43:25 AM UTC 24 Sep 11 05:43:27 AM UTC 24 29740639 ps
T831 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_glitch.2237535389 Sep 11 05:43:25 AM UTC 24 Sep 11 05:43:27 AM UTC 24 58796779 ps
T832 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_lowpower_wakeup_race.189388218 Sep 11 05:43:24 AM UTC 24 Sep 11 05:43:27 AM UTC 24 167145490 ps
T833 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_smoke.2509875790 Sep 11 05:43:42 AM UTC 24 Sep 11 05:43:44 AM UTC 24 145339782 ps
T834 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_reset_invalid.1568168340 Sep 11 05:43:42 AM UTC 24 Sep 11 05:43:44 AM UTC 24 119309878 ps
T835 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_wakeup.1927091334 Sep 11 05:43:24 AM UTC 24 Sep 11 05:43:27 AM UTC 24 300410803 ps
T836 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_global_esc.1967196931 Sep 11 05:43:25 AM UTC 24 Sep 11 05:43:27 AM UTC 24 32631987 ps
T837 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_stress_all.924934290 Sep 11 05:43:24 AM UTC 24 Sep 11 05:43:27 AM UTC 24 1286361998 ps
T838 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_wakeup_reset.3813091002 Sep 11 05:43:24 AM UTC 24 Sep 11 05:43:27 AM UTC 24 96874818 ps
T839 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_disable_rom_integrity_check.2838067602 Sep 11 05:43:25 AM UTC 24 Sep 11 05:43:27 AM UTC 24 99639106 ps
T840 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_sec_cm_rstmgr_intersig_mubi.2245293761 Sep 11 05:43:25 AM UTC 24 Sep 11 05:43:27 AM UTC 24 150270820 ps
T841 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_aborted_low_power.3774781461 Sep 11 05:43:24 AM UTC 24 Sep 11 05:43:27 AM UTC 24 29576948 ps
T842 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_reset_invalid.1860718269 Sep 11 05:43:25 AM UTC 24 Sep 11 05:43:27 AM UTC 24 101345183 ps
T843 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_escalation_timeout.4283842871 Sep 11 05:43:25 AM UTC 24 Sep 11 05:43:27 AM UTC 24 206912542 ps
T844 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_sec_cm_ctrl_config_regwen.1201129635 Sep 11 05:43:25 AM UTC 24 Sep 11 05:43:27 AM UTC 24 93038637 ps
T845 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3782185072 Sep 11 05:43:24 AM UTC 24 Sep 11 05:43:27 AM UTC 24 1550493696 ps
T846 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.820723785 Sep 11 05:43:24 AM UTC 24 Sep 11 05:43:28 AM UTC 24 874197925 ps
T847 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3194498199 Sep 11 05:43:24 AM UTC 24 Sep 11 05:43:28 AM UTC 24 857733744 ps
T848 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.670665546 Sep 11 05:43:25 AM UTC 24 Sep 11 05:43:29 AM UTC 24 840404587 ps
T849 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_stress_all.438167593 Sep 11 05:43:24 AM UTC 24 Sep 11 05:43:29 AM UTC 24 2378728384 ps
T850 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_stress_all_with_rand_reset.3882097899 Sep 11 05:43:24 AM UTC 24 Sep 11 05:43:31 AM UTC 24 10112597743 ps
T149 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_stress_all_with_rand_reset.3710458380 Sep 11 05:43:24 AM UTC 24 Sep 11 05:43:32 AM UTC 24 1893070022 ps
T851 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_lowpower_invalid.2934018524 Sep 11 05:43:41 AM UTC 24 Sep 11 05:43:43 AM UTC 24 76692858 ps
T852 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_smoke.3813070622 Sep 11 05:43:41 AM UTC 24 Sep 11 05:43:43 AM UTC 24 71332776 ps
T853 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_aborted_low_power.2724108351 Sep 11 05:43:42 AM UTC 24 Sep 11 05:43:43 AM UTC 24 25790732 ps
T854 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_wakeup.2725444896 Sep 11 05:43:41 AM UTC 24 Sep 11 05:43:43 AM UTC 24 882206969 ps
T855 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_lowpower_wakeup_race.1204818832 Sep 11 05:43:42 AM UTC 24 Sep 11 05:43:44 AM UTC 24 187347172 ps
T856 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_lowpower_wakeup_race.4291577638 Sep 11 05:43:41 AM UTC 24 Sep 11 05:43:43 AM UTC 24 147438449 ps
T857 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_esc_clk_rst_malfunc.2027750772 Sep 11 05:43:42 AM UTC 24 Sep 11 05:43:43 AM UTC 24 31616900 ps
T858 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_reset.3383827147 Sep 11 05:43:41 AM UTC 24 Sep 11 05:43:43 AM UTC 24 78436883 ps
T859 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_wakeup_reset.628395938 Sep 11 05:43:42 AM UTC 24 Sep 11 05:43:44 AM UTC 24 471962508 ps
T860 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_glitch.795921258 Sep 11 05:43:42 AM UTC 24 Sep 11 05:43:44 AM UTC 24 52151178 ps
T861 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_global_esc.1457455718 Sep 11 05:43:42 AM UTC 24 Sep 11 05:43:44 AM UTC 24 53606910 ps
T862 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_wakeup.1443661784 Sep 11 05:43:42 AM UTC 24 Sep 11 05:43:44 AM UTC 24 371614700 ps
T863 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_rstmgr_intersig_mubi.2233011508 Sep 11 05:43:42 AM UTC 24 Sep 11 05:43:44 AM UTC 24 66105443 ps
T864 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_escalation_timeout.58500917 Sep 11 05:43:42 AM UTC 24 Sep 11 05:43:44 AM UTC 24 108031191 ps
T865 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_lowpower_invalid.2295025472 Sep 11 05:43:42 AM UTC 24 Sep 11 05:43:44 AM UTC 24 77831201 ps
T866 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_global_esc.2848710958 Sep 11 05:44:18 AM UTC 24 Sep 11 05:44:21 AM UTC 24 59884794 ps
T867 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_rstmgr_intersig_mubi.2232243836 Sep 11 05:43:42 AM UTC 24 Sep 11 05:43:44 AM UTC 24 134538852 ps
T868 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_wakeup_reset.66326670 Sep 11 05:43:42 AM UTC 24 Sep 11 05:43:44 AM UTC 24 196188353 ps
T869 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_smoke.2101633288 Sep 11 05:43:43 AM UTC 24 Sep 11 05:43:44 AM UTC 24 53260425 ps
T870 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_escalation_timeout.1978122566 Sep 11 05:43:42 AM UTC 24 Sep 11 05:43:44 AM UTC 24 222718468 ps
T871 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_lowpower_invalid.1726723146 Sep 11 05:43:43 AM UTC 24 Sep 11 05:43:44 AM UTC 24 40816921 ps
T872 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_reset.1607865863 Sep 11 05:43:43 AM UTC 24 Sep 11 05:43:44 AM UTC 24 38231854 ps
T873 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_reset_invalid.2193382422 Sep 11 05:43:43 AM UTC 24 Sep 11 05:43:45 AM UTC 24 153684653 ps
T874 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_disable_rom_integrity_check.2420016975 Sep 11 05:43:42 AM UTC 24 Sep 11 05:43:45 AM UTC 24 62234623 ps
T875 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_ctrl_config_regwen.1907438731 Sep 11 05:43:42 AM UTC 24 Sep 11 05:43:45 AM UTC 24 378906192 ps
T876 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.912263918 Sep 11 05:43:42 AM UTC 24 Sep 11 05:43:45 AM UTC 24 892720088 ps
T877 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_stress_all.3540455283 Sep 11 05:43:43 AM UTC 24 Sep 11 05:43:45 AM UTC 24 457024983 ps
T878 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3000935448 Sep 11 05:43:42 AM UTC 24 Sep 11 05:43:46 AM UTC 24 867272558 ps
T879 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2600754116 Sep 11 05:43:42 AM UTC 24 Sep 11 05:43:46 AM UTC 24 858885919 ps
T880 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3674418805 Sep 11 05:43:42 AM UTC 24 Sep 11 05:43:46 AM UTC 24 801510296 ps
T881 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_stress_all.3694197711 Sep 11 05:43:41 AM UTC 24 Sep 11 05:43:46 AM UTC 24 8548279273 ps
T882 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_stress_all.434805890 Sep 11 05:43:42 AM UTC 24 Sep 11 05:43:47 AM UTC 24 2471611914 ps
T883 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_stress_all_with_rand_reset.2686690363 Sep 11 05:43:41 AM UTC 24 Sep 11 05:43:58 AM UTC 24 17105802795 ps
T884 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_reset.1296208515 Sep 11 05:44:18 AM UTC 24 Sep 11 05:44:20 AM UTC 24 79290227 ps
T885 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_wakeup.3796178599 Sep 11 05:43:59 AM UTC 24 Sep 11 05:44:01 AM UTC 24 59957724 ps
T886 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_global_esc.3462608216 Sep 11 05:44:00 AM UTC 24 Sep 11 05:44:01 AM UTC 24 33034556 ps
T887 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_esc_clk_rst_malfunc.2658913526 Sep 11 05:44:00 AM UTC 24 Sep 11 05:44:01 AM UTC 24 31556302 ps
T888 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_aborted_low_power.2929883889 Sep 11 05:43:59 AM UTC 24 Sep 11 05:44:01 AM UTC 24 45181998 ps
T889 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_wakeup_reset.2632041985 Sep 11 05:43:59 AM UTC 24 Sep 11 05:44:01 AM UTC 24 380654042 ps
T890 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_glitch.1315757404 Sep 11 05:44:00 AM UTC 24 Sep 11 05:44:01 AM UTC 24 50077695 ps
T891 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_ctrl_config_regwen.2654243438 Sep 11 05:44:00 AM UTC 24 Sep 11 05:44:01 AM UTC 24 223475712 ps
T892 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_escalation_timeout.269498320 Sep 11 05:44:00 AM UTC 24 Sep 11 05:44:01 AM UTC 24 672155188 ps
T893 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_rstmgr_intersig_mubi.4069089505 Sep 11 05:44:00 AM UTC 24 Sep 11 05:44:01 AM UTC 24 142308082 ps
T894 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_disable_rom_integrity_check.1646116453 Sep 11 05:44:00 AM UTC 24 Sep 11 05:44:01 AM UTC 24 63848050 ps
T895 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_lowpower_wakeup_race.780452442 Sep 11 05:43:59 AM UTC 24 Sep 11 05:44:01 AM UTC 24 298586341 ps
T896 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_lowpower_invalid.969107003 Sep 11 05:44:00 AM UTC 24 Sep 11 05:44:01 AM UTC 24 70244042 ps
T897 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_smoke.1415712443 Sep 11 05:44:00 AM UTC 24 Sep 11 05:44:02 AM UTC 24 113224410 ps
T898 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_reset_invalid.223287459 Sep 11 05:44:00 AM UTC 24 Sep 11 05:44:02 AM UTC 24 208730590 ps
T899 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_global_esc.3631316580 Sep 11 05:44:00 AM UTC 24 Sep 11 05:44:02 AM UTC 24 32831568 ps
T900 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_stress_all.698296959 Sep 11 05:44:00 AM UTC 24 Sep 11 05:44:02 AM UTC 24 83508929 ps
T901 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_aborted_low_power.3650463651 Sep 11 05:44:00 AM UTC 24 Sep 11 05:44:02 AM UTC 24 20266598 ps
T902 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_reset.4233549937 Sep 11 05:44:00 AM UTC 24 Sep 11 05:44:02 AM UTC 24 101269182 ps
T903 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_esc_clk_rst_malfunc.1754410186 Sep 11 05:44:00 AM UTC 24 Sep 11 05:44:02 AM UTC 24 29772448 ps
T904 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_disable_rom_integrity_check.3007410917 Sep 11 05:44:00 AM UTC 24 Sep 11 05:44:02 AM UTC 24 54761370 ps
T905 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_reset_invalid.2965690619 Sep 11 05:44:18 AM UTC 24 Sep 11 05:44:21 AM UTC 24 98051744 ps
T906 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_wakeup_reset.1387299598 Sep 11 05:44:00 AM UTC 24 Sep 11 05:44:02 AM UTC 24 328649897 ps
T907 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_sec_cm_rstmgr_intersig_mubi.979719767 Sep 11 05:44:00 AM UTC 24 Sep 11 05:44:02 AM UTC 24 109655089 ps
T908 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_lowpower_wakeup_race.2666144664 Sep 11 05:44:00 AM UTC 24 Sep 11 05:44:02 AM UTC 24 138898459 ps
T909 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_glitch.2073104351 Sep 11 05:44:00 AM UTC 24 Sep 11 05:44:02 AM UTC 24 32810378 ps
T910 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_sec_cm_ctrl_config_regwen.2928173576 Sep 11 05:44:00 AM UTC 24 Sep 11 05:44:02 AM UTC 24 81570224 ps
T911 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_lowpower_invalid.2572271138 Sep 11 05:44:00 AM UTC 24 Sep 11 05:44:02 AM UTC 24 76317974 ps
T912 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_smoke.514496993 Sep 11 05:44:00 AM UTC 24 Sep 11 05:44:02 AM UTC 24 33534388 ps
T913 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_escalation_timeout.229095043 Sep 11 05:44:00 AM UTC 24 Sep 11 05:44:02 AM UTC 24 114805073 ps
T914 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_wakeup_reset.1344564354 Sep 11 05:44:01 AM UTC 24 Sep 11 05:44:02 AM UTC 24 43980100 ps
T915 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_reset_invalid.3258339987 Sep 11 05:44:00 AM UTC 24 Sep 11 05:44:02 AM UTC 24 109836138 ps
T916 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_reset.3437677725 Sep 11 05:44:00 AM UTC 24 Sep 11 05:44:03 AM UTC 24 63392354 ps
T917 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_wakeup.2250448739 Sep 11 05:44:00 AM UTC 24 Sep 11 05:44:03 AM UTC 24 292392258 ps
T918 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_wakeup.368612046 Sep 11 05:44:01 AM UTC 24 Sep 11 05:44:03 AM UTC 24 168415277 ps
T919 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_lowpower_wakeup_race.2441722142 Sep 11 05:44:01 AM UTC 24 Sep 11 05:44:03 AM UTC 24 152519443 ps
T920 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.213615238 Sep 11 05:44:00 AM UTC 24 Sep 11 05:44:03 AM UTC 24 1115851883 ps
T921 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2562477555 Sep 11 05:43:59 AM UTC 24 Sep 11 05:44:03 AM UTC 24 846025381 ps
T922 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3174311821 Sep 11 05:44:00 AM UTC 24 Sep 11 05:44:04 AM UTC 24 914726585 ps
T923 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.585297914 Sep 11 05:43:59 AM UTC 24 Sep 11 05:44:04 AM UTC 24 818894055 ps
T924 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_stress_all_with_rand_reset.4137601153 Sep 11 05:43:43 AM UTC 24 Sep 11 05:44:04 AM UTC 24 4964428810 ps
T925 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_stress_all.1547140588 Sep 11 05:44:00 AM UTC 24 Sep 11 05:44:06 AM UTC 24 3682992902 ps
T48 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_stress_all_with_rand_reset.2953263373 Sep 11 05:43:42 AM UTC 24 Sep 11 05:44:09 AM UTC 24 11850170409 ps
T56 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_stress_all_with_rand_reset.751479037 Sep 11 05:44:00 AM UTC 24 Sep 11 05:44:10 AM UTC 24 2153143806 ps
T926 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_stress_all_with_rand_reset.107361519 Sep 11 05:44:00 AM UTC 24 Sep 11 05:44:14 AM UTC 24 8440351015 ps
T927 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_global_esc.504321310 Sep 11 05:44:18 AM UTC 24 Sep 11 05:44:20 AM UTC 24 32320540 ps
T928 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_esc_clk_rst_malfunc.1055309815 Sep 11 05:44:18 AM UTC 24 Sep 11 05:44:20 AM UTC 24 30187051 ps
T929 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_aborted_low_power.221010148 Sep 11 05:44:18 AM UTC 24 Sep 11 05:44:20 AM UTC 24 31301478 ps
T930 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_escalation_timeout.2297842218 Sep 11 05:44:18 AM UTC 24 Sep 11 05:44:20 AM UTC 24 206114808 ps
T931 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_esc_clk_rst_malfunc.932587662 Sep 11 05:44:18 AM UTC 24 Sep 11 05:44:21 AM UTC 24 39192225 ps
T932 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_glitch.3964502887 Sep 11 05:44:18 AM UTC 24 Sep 11 05:44:20 AM UTC 24 64892201 ps
T933 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_sec_cm_rstmgr_intersig_mubi.109081283 Sep 11 05:44:18 AM UTC 24 Sep 11 05:44:20 AM UTC 24 226444166 ps
T934 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_lowpower_invalid.1413488098 Sep 11 05:44:18 AM UTC 24 Sep 11 05:44:20 AM UTC 24 83001995 ps
T935 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_disable_rom_integrity_check.3056163510 Sep 11 05:44:18 AM UTC 24 Sep 11 05:44:20 AM UTC 24 77176534 ps
T936 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_smoke.1208998476 Sep 11 05:44:18 AM UTC 24 Sep 11 05:44:20 AM UTC 24 74417837 ps
T937 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_sec_cm_ctrl_config_regwen.2851650453 Sep 11 05:44:18 AM UTC 24 Sep 11 05:44:20 AM UTC 24 160925893 ps
T938 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_aborted_low_power.2593214720 Sep 11 05:44:18 AM UTC 24 Sep 11 05:44:21 AM UTC 24 31322267 ps
T939 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_lowpower_invalid.3651145224 Sep 11 05:44:19 AM UTC 24 Sep 11 05:44:21 AM UTC 24 77947158 ps
T940 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_glitch.100015729 Sep 11 05:44:18 AM UTC 24 Sep 11 05:44:21 AM UTC 24 41984965 ps
T941 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_lowpower_wakeup_race.2372800956 Sep 11 05:44:18 AM UTC 24 Sep 11 05:44:21 AM UTC 24 274282624 ps
T942 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_rstmgr_intersig_mubi.1805773582 Sep 11 05:44:18 AM UTC 24 Sep 11 05:44:21 AM UTC 24 53551443 ps
T943 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_escalation_timeout.3052372967 Sep 11 05:44:18 AM UTC 24 Sep 11 05:44:21 AM UTC 24 114300954 ps
T944 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_disable_rom_integrity_check.1939229394 Sep 11 05:44:18 AM UTC 24 Sep 11 05:44:21 AM UTC 24 48956822 ps
T945 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_wakeup.1049368502 Sep 11 05:44:18 AM UTC 24 Sep 11 05:44:21 AM UTC 24 164135495 ps
T946 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_wakeup_reset.1279930992 Sep 11 05:44:18 AM UTC 24 Sep 11 05:44:21 AM UTC 24 251313577 ps
T947 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_wakeup_reset.1775234614 Sep 11 05:44:19 AM UTC 24 Sep 11 05:44:21 AM UTC 24 143515243 ps
T948 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_smoke.3872412746 Sep 11 05:44:19 AM UTC 24 Sep 11 05:44:21 AM UTC 24 65801671 ps
T949 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_ctrl_config_regwen.3048523918 Sep 11 05:44:18 AM UTC 24 Sep 11 05:44:21 AM UTC 24 271442486 ps
T950 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_reset_invalid.1199782646 Sep 11 05:44:18 AM UTC 24 Sep 11 05:44:21 AM UTC 24 118806611 ps
T951 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_wakeup.2713503152 Sep 11 05:44:19 AM UTC 24 Sep 11 05:44:21 AM UTC 24 296355945 ps
T952 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_stress_all.2135821173 Sep 11 05:44:19 AM UTC 24 Sep 11 05:44:21 AM UTC 24 232630968 ps
T953 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_esc_clk_rst_malfunc.713734760 Sep 11 05:44:19 AM UTC 24 Sep 11 05:44:21 AM UTC 24 28651632 ps
T954 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_aborted_low_power.3229345859 Sep 11 05:44:19 AM UTC 24 Sep 11 05:44:21 AM UTC 24 23971482 ps
T955 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_reset.4186682894 Sep 11 05:44:19 AM UTC 24 Sep 11 05:44:21 AM UTC 24 47062735 ps
T956 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_rstmgr_intersig_mubi.4105158196 Sep 11 05:44:19 AM UTC 24 Sep 11 05:44:21 AM UTC 24 142463746 ps
T957 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_lowpower_wakeup_race.2248176176 Sep 11 05:44:19 AM UTC 24 Sep 11 05:44:22 AM UTC 24 296308405 ps
T958 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3700002471 Sep 11 05:44:18 AM UTC 24 Sep 11 05:44:22 AM UTC 24 1318633943 ps
T959 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.502323819 Sep 11 05:44:18 AM UTC 24 Sep 11 05:44:22 AM UTC 24 1528763799 ps
T960 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_stress_all.310600236 Sep 11 05:44:18 AM UTC 24 Sep 11 05:44:22 AM UTC 24 1178326133 ps
T961 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2130413288 Sep 11 05:44:18 AM UTC 24 Sep 11 05:44:22 AM UTC 24 935512569 ps
T962 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.42236786 Sep 11 05:44:19 AM UTC 24 Sep 11 05:44:23 AM UTC 24 1216173995 ps
T963 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3259854518 Sep 11 05:44:19 AM UTC 24 Sep 11 05:44:23 AM UTC 24 1032100865 ps
T964 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_stress_all_with_rand_reset.1098216395 Sep 11 05:44:19 AM UTC 24 Sep 11 05:44:23 AM UTC 24 1644506406 ps
T965 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_stress_all_with_rand_reset.1608757032 Sep 11 05:44:18 AM UTC 24 Sep 11 05:44:32 AM UTC 24 2869928421 ps
T966 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_global_esc.1152378234 Sep 11 05:44:39 AM UTC 24 Sep 11 05:44:40 AM UTC 24 160371202 ps
T967 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_ctrl_config_regwen.1727872381 Sep 11 05:44:39 AM UTC 24 Sep 11 05:44:40 AM UTC 24 86897766 ps
T968 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_glitch.3281200701 Sep 11 05:44:39 AM UTC 24 Sep 11 05:44:40 AM UTC 24 54696504 ps
T969 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_escalation_timeout.3894610097 Sep 11 05:44:39 AM UTC 24 Sep 11 05:44:40 AM UTC 24 207354623 ps
T970 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_smoke.941040042 Sep 11 05:44:39 AM UTC 24 Sep 11 05:44:40 AM UTC 24 63719349 ps
T971 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_lowpower_invalid.3694608860 Sep 11 05:44:39 AM UTC 24 Sep 11 05:44:40 AM UTC 24 154563668 ps
T972 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_disable_rom_integrity_check.3957402978 Sep 11 05:44:39 AM UTC 24 Sep 11 05:44:41 AM UTC 24 68412519 ps
T973 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_reset.3532325193 Sep 11 05:44:39 AM UTC 24 Sep 11 05:44:41 AM UTC 24 49625921 ps
T974 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_reset_invalid.3607452299 Sep 11 05:44:39 AM UTC 24 Sep 11 05:44:41 AM UTC 24 117022288 ps
T975 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_lowpower_wakeup_race.488996579 Sep 11 05:44:39 AM UTC 24 Sep 11 05:44:41 AM UTC 24 79859591 ps
T976 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_esc_clk_rst_malfunc.400236719 Sep 11 05:44:39 AM UTC 24 Sep 11 05:44:41 AM UTC 24 33102123 ps
T977 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_wakeup.556880284 Sep 11 05:44:39 AM UTC 24 Sep 11 05:44:41 AM UTC 24 226767718 ps
T978 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_wakeup_reset.3545276068 Sep 11 05:44:39 AM UTC 24 Sep 11 05:44:41 AM UTC 24 71329179 ps
T979 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_global_esc.1131321633 Sep 11 05:44:39 AM UTC 24 Sep 11 05:44:41 AM UTC 24 62056605 ps
T980 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_aborted_low_power.117455533 Sep 11 05:44:39 AM UTC 24 Sep 11 05:44:41 AM UTC 24 124721596 ps
T981 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_ctrl_config_regwen.2305346500 Sep 11 05:44:39 AM UTC 24 Sep 11 05:44:41 AM UTC 24 155885550 ps
T982 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_glitch.473109403 Sep 11 05:44:39 AM UTC 24 Sep 11 05:44:41 AM UTC 24 65599977 ps
T983 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_rstmgr_intersig_mubi.1449622428 Sep 11 05:44:39 AM UTC 24 Sep 11 05:44:41 AM UTC 24 118973572 ps
T984 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_escalation_timeout.1259581046 Sep 11 05:44:39 AM UTC 24 Sep 11 05:44:41 AM UTC 24 201828391 ps
T985 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_reset_invalid.3616597848 Sep 11 05:44:39 AM UTC 24 Sep 11 05:44:41 AM UTC 24 171814281 ps
T986 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_disable_rom_integrity_check.3940186963 Sep 11 05:44:39 AM UTC 24 Sep 11 05:44:41 AM UTC 24 66193589 ps
T987 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_lowpower_invalid.2079405254 Sep 11 05:44:39 AM UTC 24 Sep 11 05:44:41 AM UTC 24 43401451 ps
T988 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_stress_all_with_rand_reset.3656954537 Sep 11 05:44:39 AM UTC 24 Sep 11 05:44:44 AM UTC 24 407035082 ps
T989 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2793420646 Sep 11 05:44:39 AM UTC 24 Sep 11 05:44:44 AM UTC 24 929711785 ps
T990 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3514450809 Sep 11 05:44:39 AM UTC 24 Sep 11 05:44:44 AM UTC 24 761751727 ps
T991 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_stress_all.222537689 Sep 11 05:44:39 AM UTC 24 Sep 11 05:44:44 AM UTC 24 1508601917 ps
T992 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_stress_all.2718736614 Sep 11 05:44:39 AM UTC 24 Sep 11 05:44:46 AM UTC 24 1382714467 ps
T150 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_stress_all_with_rand_reset.2585300701 Sep 11 05:44:39 AM UTC 24 Sep 11 05:44:51 AM UTC 24 3157590841 ps
T57 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_intr_test.1136415683 Sep 11 05:08:26 AM UTC 24 Sep 11 05:08:28 AM UTC 24 17069640 ps
T49 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.1774240949 Sep 11 05:08:26 AM UTC 24 Sep 11 05:08:28 AM UTC 24 262990973 ps
T54 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_tl_errors.392307633 Sep 11 05:08:26 AM UTC 24 Sep 11 05:08:29 AM UTC 24 106667344 ps
T63 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.2705459580 Sep 11 05:08:27 AM UTC 24 Sep 11 05:08:29 AM UTC 24 56016167 ps
T66 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_rw.1109725075 Sep 11 05:08:27 AM UTC 24 Sep 11 05:08:29 AM UTC 24 25041932 ps
T64 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.2157917545 Sep 11 05:08:27 AM UTC 24 Sep 11 05:08:29 AM UTC 24 27052020 ps
T65 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_intr_test.760996813 Sep 11 05:08:29 AM UTC 24 Sep 11 05:08:30 AM UTC 24 16398399 ps
T61 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.4157459489 Sep 11 05:08:29 AM UTC 24 Sep 11 05:08:30 AM UTC 24 200571942 ps
T62 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.803205663 Sep 11 05:08:28 AM UTC 24 Sep 11 05:08:31 AM UTC 24 33786481 ps
T50 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.3133701489 Sep 11 05:08:29 AM UTC 24 Sep 11 05:08:31 AM UTC 24 42546689 ps
T55 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_tl_errors.2776297334 Sep 11 05:08:29 AM UTC 24 Sep 11 05:08:31 AM UTC 24 97923424 ps
T189 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.1969488000 Sep 11 05:08:27 AM UTC 24 Sep 11 05:08:31 AM UTC 24 937338952 ps
T58 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.3412953470 Sep 11 05:08:29 AM UTC 24 Sep 11 05:08:31 AM UTC 24 259026087 ps
T110 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_rw.4247288289 Sep 11 05:08:30 AM UTC 24 Sep 11 05:08:32 AM UTC 24 18786677 ps
T182 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_intr_test.2835378699 Sep 11 05:08:30 AM UTC 24 Sep 11 05:08:32 AM UTC 24 126895242 ps
T993 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.665513051 Sep 11 05:08:30 AM UTC 24 Sep 11 05:08:32 AM UTC 24 46167642 ps
T111 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.3090520064 Sep 11 05:08:30 AM UTC 24 Sep 11 05:08:32 AM UTC 24 38902659 ps
T994 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.3824947902 Sep 11 05:08:30 AM UTC 24 Sep 11 05:08:32 AM UTC 24 59138087 ps
T125 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.1922907534 Sep 11 05:08:30 AM UTC 24 Sep 11 05:08:32 AM UTC 24 76323500 ps
T59 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.1455280769 Sep 11 05:08:30 AM UTC 24 Sep 11 05:08:32 AM UTC 24 96635377 ps
T68 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_tl_errors.2553116507 Sep 11 05:08:30 AM UTC 24 Sep 11 05:08:33 AM UTC 24 48699539 ps
T126 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_rw.1408108705 Sep 11 05:08:31 AM UTC 24 Sep 11 05:08:33 AM UTC 24 17475965 ps
T69 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.3803444682 Sep 11 05:08:38 AM UTC 24 Sep 11 05:08:40 AM UTC 24 286178462 ps
T119 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.2290492052 Sep 11 05:08:30 AM UTC 24 Sep 11 05:08:33 AM UTC 24 774849153 ps
T995 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.724309578 Sep 11 05:08:32 AM UTC 24 Sep 11 05:08:34 AM UTC 24 63844388 ps
T127 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.3730633464 Sep 11 05:08:31 AM UTC 24 Sep 11 05:08:34 AM UTC 24 62034433 ps
T112 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.774229351 Sep 11 05:08:31 AM UTC 24 Sep 11 05:08:34 AM UTC 24 41891610 ps
T996 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.2031328154 Sep 11 05:08:31 AM UTC 24 Sep 11 05:08:34 AM UTC 24 190559125 ps
T183 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_intr_test.3421373637 Sep 11 05:08:33 AM UTC 24 Sep 11 05:08:34 AM UTC 24 56464804 ps
T113 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_rw.550645117 Sep 11 05:08:33 AM UTC 24 Sep 11 05:08:35 AM UTC 24 20101376 ps
T997 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.2335191824 Sep 11 05:08:33 AM UTC 24 Sep 11 05:08:35 AM UTC 24 26760740 ps
T70 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_tl_errors.2710810443 Sep 11 05:08:32 AM UTC 24 Sep 11 05:08:35 AM UTC 24 79224116 ps
T998 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.2878253049 Sep 11 05:08:33 AM UTC 24 Sep 11 05:08:35 AM UTC 24 66737821 ps
T128 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.1524948867 Sep 11 05:08:33 AM UTC 24 Sep 11 05:08:35 AM UTC 24 224621617 ps
T114 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.3945348400 Sep 11 05:08:33 AM UTC 24 Sep 11 05:08:35 AM UTC 24 138904124 ps
T170 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.3160155817 Sep 11 05:08:33 AM UTC 24 Sep 11 05:08:35 AM UTC 24 211410117 ps
T999 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_tl_errors.2719419246 Sep 11 05:08:33 AM UTC 24 Sep 11 05:08:35 AM UTC 24 193534039 ps
T184 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_intr_test.3913266010 Sep 11 05:08:34 AM UTC 24 Sep 11 05:08:36 AM UTC 24 18489460 ps
T115 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.2955078418 Sep 11 05:08:34 AM UTC 24 Sep 11 05:08:36 AM UTC 24 57006818 ps
T116 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_rw.626364288 Sep 11 05:08:34 AM UTC 24 Sep 11 05:08:36 AM UTC 24 23289635 ps
T129 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.2458628345 Sep 11 05:08:35 AM UTC 24 Sep 11 05:08:36 AM UTC 24 18834197 ps
T185 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_intr_test.1782389182 Sep 11 05:08:35 AM UTC 24 Sep 11 05:08:36 AM UTC 24 20393765 ps
T1000 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.3156952243 Sep 11 05:08:34 AM UTC 24 Sep 11 05:08:37 AM UTC 24 94803387 ps
T1001 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.3742280216 Sep 11 05:08:35 AM UTC 24 Sep 11 05:08:37 AM UTC 24 53424792 ps
T172 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.2279945970 Sep 11 05:08:34 AM UTC 24 Sep 11 05:08:37 AM UTC 24 1473154092 ps
T171 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.2083761294 Sep 11 05:08:35 AM UTC 24 Sep 11 05:08:37 AM UTC 24 160055520 ps
T1002 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.2440557031 Sep 11 05:08:33 AM UTC 24 Sep 11 05:08:37 AM UTC 24 211498211 ps
T130 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.3951142832 Sep 11 05:08:36 AM UTC 24 Sep 11 05:08:38 AM UTC 24 21183066 ps
T1003 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.139360200 Sep 11 05:08:38 AM UTC 24 Sep 11 05:08:40 AM UTC 24 40196416 ps
T1004 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_csr_rw.1018037846 Sep 11 05:08:36 AM UTC 24 Sep 11 05:08:38 AM UTC 24 53184728 ps
T1005 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.169403152 Sep 11 05:08:36 AM UTC 24 Sep 11 05:08:38 AM UTC 24 79084961 ps
T1006 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_csr_rw.346577680 Sep 11 05:08:36 AM UTC 24 Sep 11 05:08:38 AM UTC 24 22057809 ps
T186 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_intr_test.43871356 Sep 11 05:08:36 AM UTC 24 Sep 11 05:08:38 AM UTC 24 18006655 ps
T1007 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_tl_errors.4026809496 Sep 11 05:08:35 AM UTC 24 Sep 11 05:08:38 AM UTC 24 421191064 ps
T1008 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_csr_rw.1223855782 Sep 11 05:08:36 AM UTC 24 Sep 11 05:08:38 AM UTC 24 20201560 ps
T188 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_intr_test.227768236 Sep 11 05:08:36 AM UTC 24 Sep 11 05:08:38 AM UTC 24 19439356 ps
T1009 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.3020424813 Sep 11 05:08:36 AM UTC 24 Sep 11 05:08:38 AM UTC 24 48616528 ps
T1010 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.1748665041 Sep 11 05:08:36 AM UTC 24 Sep 11 05:08:38 AM UTC 24 45849179 ps
T1011 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_tl_errors.3055233365 Sep 11 05:08:36 AM UTC 24 Sep 11 05:08:39 AM UTC 24 53404795 ps
T173 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.734433904 Sep 11 05:08:36 AM UTC 24 Sep 11 05:08:39 AM UTC 24 205485510 ps
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