| T806 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_disable_rom_integrity_check.2796928487 |
|
|
Sep 18 07:49:56 PM UTC 24 |
Sep 18 07:49:59 PM UTC 24 |
62929876 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_escalation_timeout.3011211623 |
|
|
Sep 18 07:49:56 PM UTC 24 |
Sep 18 07:49:59 PM UTC 24 |
404622022 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_lowpower_invalid.3062189172 |
|
|
Sep 18 07:49:53 PM UTC 24 |
Sep 18 07:49:59 PM UTC 24 |
41684047 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1426404016 |
|
|
Sep 18 07:49:55 PM UTC 24 |
Sep 18 07:50:00 PM UTC 24 |
1196151659 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_smoke.1713119256 |
|
|
Sep 18 07:49:55 PM UTC 24 |
Sep 18 07:50:00 PM UTC 24 |
64699599 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3717069450 |
|
|
Sep 18 07:49:50 PM UTC 24 |
Sep 18 07:50:00 PM UTC 24 |
1141309292 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3554712092 |
|
|
Sep 18 07:49:55 PM UTC 24 |
Sep 18 07:50:01 PM UTC 24 |
774218380 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_lowpower_invalid.1151115892 |
|
|
Sep 18 07:49:59 PM UTC 24 |
Sep 18 07:50:01 PM UTC 24 |
55596465 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_smoke.2768735291 |
|
|
Sep 18 07:49:59 PM UTC 24 |
Sep 18 07:50:01 PM UTC 24 |
28995289 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_wakeup.864703720 |
|
|
Sep 18 07:49:59 PM UTC 24 |
Sep 18 07:50:01 PM UTC 24 |
186271616 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_aborted_low_power.3618084379 |
|
|
Sep 18 07:49:59 PM UTC 24 |
Sep 18 07:50:01 PM UTC 24 |
26451109 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_reset_invalid.4218479086 |
|
|
Sep 18 07:49:59 PM UTC 24 |
Sep 18 07:50:01 PM UTC 24 |
96866661 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_esc_clk_rst_malfunc.4073342472 |
|
|
Sep 18 07:50:00 PM UTC 24 |
Sep 18 07:50:02 PM UTC 24 |
45344444 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_reset.2199227012 |
|
|
Sep 18 07:49:59 PM UTC 24 |
Sep 18 07:50:02 PM UTC 24 |
74956088 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_lowpower_wakeup_race.20016314 |
|
|
Sep 18 07:49:59 PM UTC 24 |
Sep 18 07:50:02 PM UTC 24 |
175874297 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_sec_cm_rstmgr_intersig_mubi.2715367240 |
|
|
Sep 18 07:50:00 PM UTC 24 |
Sep 18 07:50:02 PM UTC 24 |
76297402 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_wakeup_reset.522931664 |
|
|
Sep 18 07:49:59 PM UTC 24 |
Sep 18 07:50:02 PM UTC 24 |
204651863 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_global_esc.2111346795 |
|
|
Sep 18 07:50:01 PM UTC 24 |
Sep 18 07:50:03 PM UTC 24 |
70839468 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_glitch.1765096894 |
|
|
Sep 18 07:50:01 PM UTC 24 |
Sep 18 07:50:03 PM UTC 24 |
50191802 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_sec_cm_ctrl_config_regwen.2075951123 |
|
|
Sep 18 07:50:01 PM UTC 24 |
Sep 18 07:50:03 PM UTC 24 |
206891763 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_escalation_timeout.3317823332 |
|
|
Sep 18 07:50:01 PM UTC 24 |
Sep 18 07:50:03 PM UTC 24 |
111693275 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2974292210 |
|
|
Sep 18 07:50:00 PM UTC 24 |
Sep 18 07:50:03 PM UTC 24 |
1768944118 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_disable_rom_integrity_check.3050581880 |
|
|
Sep 18 07:50:01 PM UTC 24 |
Sep 18 07:50:03 PM UTC 24 |
50818726 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.276077437 |
|
|
Sep 18 07:50:00 PM UTC 24 |
Sep 18 07:50:04 PM UTC 24 |
825017964 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_stress_all.2005295376 |
|
|
Sep 18 07:49:59 PM UTC 24 |
Sep 18 07:50:04 PM UTC 24 |
1350758081 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_lowpower_invalid.3924968105 |
|
|
Sep 18 07:50:03 PM UTC 24 |
Sep 18 07:50:04 PM UTC 24 |
43312584 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_smoke.2905951128 |
|
|
Sep 18 07:50:03 PM UTC 24 |
Sep 18 07:50:05 PM UTC 24 |
52034613 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_reset_invalid.253977499 |
|
|
Sep 18 07:50:03 PM UTC 24 |
Sep 18 07:50:05 PM UTC 24 |
93345943 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_lowpower_wakeup_race.474716091 |
|
|
Sep 18 07:50:03 PM UTC 24 |
Sep 18 07:50:05 PM UTC 24 |
61411901 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_reset.3836691009 |
|
|
Sep 18 07:50:03 PM UTC 24 |
Sep 18 07:50:05 PM UTC 24 |
84784003 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_aborted_low_power.4009784543 |
|
|
Sep 18 07:50:03 PM UTC 24 |
Sep 18 07:50:05 PM UTC 24 |
42870192 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_wakeup.3977399877 |
|
|
Sep 18 07:50:03 PM UTC 24 |
Sep 18 07:50:06 PM UTC 24 |
148147880 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_wakeup_reset.1762693493 |
|
|
Sep 18 07:50:03 PM UTC 24 |
Sep 18 07:50:06 PM UTC 24 |
314469068 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_stress_all_with_rand_reset.3395682635 |
|
|
Sep 18 07:49:48 PM UTC 24 |
Sep 18 07:50:07 PM UTC 24 |
8263664872 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_stress_all.1972306496 |
|
|
Sep 18 07:49:55 PM UTC 24 |
Sep 18 07:50:07 PM UTC 24 |
2460870987 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3390878888 |
|
|
Sep 18 07:50:03 PM UTC 24 |
Sep 18 07:50:07 PM UTC 24 |
729110874 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_esc_clk_rst_malfunc.3446427385 |
|
|
Sep 18 07:50:05 PM UTC 24 |
Sep 18 07:50:08 PM UTC 24 |
29781593 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_sec_cm_rstmgr_intersig_mubi.3373535247 |
|
|
Sep 18 07:50:05 PM UTC 24 |
Sep 18 07:50:08 PM UTC 24 |
589562990 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_sec_cm_ctrl_config_regwen.600380277 |
|
|
Sep 18 07:50:05 PM UTC 24 |
Sep 18 07:50:08 PM UTC 24 |
33420768 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_global_esc.1029984226 |
|
|
Sep 18 07:50:05 PM UTC 24 |
Sep 18 07:50:08 PM UTC 24 |
54941803 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_glitch.1685498035 |
|
|
Sep 18 07:50:05 PM UTC 24 |
Sep 18 07:50:08 PM UTC 24 |
63180841 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_escalation_timeout.100528561 |
|
|
Sep 18 07:50:05 PM UTC 24 |
Sep 18 07:50:08 PM UTC 24 |
109189801 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_lowpower_invalid.2951104002 |
|
|
Sep 18 07:50:06 PM UTC 24 |
Sep 18 07:50:08 PM UTC 24 |
56575497 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_disable_rom_integrity_check.2888551495 |
|
|
Sep 18 07:50:06 PM UTC 24 |
Sep 18 07:50:09 PM UTC 24 |
54218084 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_smoke.1017064093 |
|
|
Sep 18 07:50:07 PM UTC 24 |
Sep 18 07:50:09 PM UTC 24 |
32854032 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_reset.328834997 |
|
|
Sep 18 07:50:07 PM UTC 24 |
Sep 18 07:50:09 PM UTC 24 |
170589437 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_wakeup.2429583531 |
|
|
Sep 18 07:50:07 PM UTC 24 |
Sep 18 07:50:09 PM UTC 24 |
130620236 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_reset_invalid.1801748928 |
|
|
Sep 18 07:50:06 PM UTC 24 |
Sep 18 07:50:09 PM UTC 24 |
97625968 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_lowpower_wakeup_race.3446254524 |
|
|
Sep 18 07:50:07 PM UTC 24 |
Sep 18 07:50:09 PM UTC 24 |
318654736 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4100037538 |
|
|
Sep 18 07:50:05 PM UTC 24 |
Sep 18 07:50:10 PM UTC 24 |
936885286 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_aborted_low_power.2822206322 |
|
|
Sep 18 07:50:08 PM UTC 24 |
Sep 18 07:50:10 PM UTC 24 |
71901599 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_wakeup_reset.4215679251 |
|
|
Sep 18 07:50:08 PM UTC 24 |
Sep 18 07:50:10 PM UTC 24 |
183552802 ps |
| T140 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_stress_all_with_rand_reset.46358804 |
|
|
Sep 18 07:50:03 PM UTC 24 |
Sep 18 07:50:11 PM UTC 24 |
4800795244 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_stress_all.3237729990 |
|
|
Sep 18 07:50:03 PM UTC 24 |
Sep 18 07:50:11 PM UTC 24 |
1445969618 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_stress_all_with_rand_reset.973489097 |
|
|
Sep 18 07:49:55 PM UTC 24 |
Sep 18 07:50:11 PM UTC 24 |
10932579885 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4106861531 |
|
|
Sep 18 07:50:08 PM UTC 24 |
Sep 18 07:50:12 PM UTC 24 |
1061731587 ps |
| T141 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_stress_all_with_rand_reset.1134382635 |
|
|
Sep 18 07:49:59 PM UTC 24 |
Sep 18 07:50:13 PM UTC 24 |
5361040148 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_global_esc.3919238455 |
|
|
Sep 18 07:50:10 PM UTC 24 |
Sep 18 07:50:13 PM UTC 24 |
31190493 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_glitch.340446863 |
|
|
Sep 18 07:50:10 PM UTC 24 |
Sep 18 07:50:13 PM UTC 24 |
54767674 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_disable_rom_integrity_check.127050132 |
|
|
Sep 18 07:50:10 PM UTC 24 |
Sep 18 07:50:13 PM UTC 24 |
49658560 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_lowpower_invalid.1374516544 |
|
|
Sep 18 07:50:10 PM UTC 24 |
Sep 18 07:50:13 PM UTC 24 |
233350697 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_smoke.2177126517 |
|
|
Sep 18 07:50:10 PM UTC 24 |
Sep 18 07:50:13 PM UTC 24 |
30478363 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_escalation_timeout.1888296755 |
|
|
Sep 18 07:50:10 PM UTC 24 |
Sep 18 07:50:13 PM UTC 24 |
202071275 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_esc_clk_rst_malfunc.1707764441 |
|
|
Sep 18 07:50:08 PM UTC 24 |
Sep 18 07:50:13 PM UTC 24 |
30524972 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_ctrl_config_regwen.2390247762 |
|
|
Sep 18 07:50:08 PM UTC 24 |
Sep 18 07:50:13 PM UTC 24 |
59798845 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_wakeup.665527597 |
|
|
Sep 18 07:50:11 PM UTC 24 |
Sep 18 07:50:13 PM UTC 24 |
46055388 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_reset_invalid.3756935212 |
|
|
Sep 18 07:50:10 PM UTC 24 |
Sep 18 07:50:13 PM UTC 24 |
110751878 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_rstmgr_intersig_mubi.4130106127 |
|
|
Sep 18 07:50:08 PM UTC 24 |
Sep 18 07:50:14 PM UTC 24 |
124105807 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_reset.1659112195 |
|
|
Sep 18 07:50:11 PM UTC 24 |
Sep 18 07:50:14 PM UTC 24 |
119969509 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_wakeup_reset.552736949 |
|
|
Sep 18 07:50:12 PM UTC 24 |
Sep 18 07:50:14 PM UTC 24 |
154147886 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_aborted_low_power.2460508770 |
|
|
Sep 18 07:50:12 PM UTC 24 |
Sep 18 07:50:14 PM UTC 24 |
28762852 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_lowpower_wakeup_race.301009144 |
|
|
Sep 18 07:50:11 PM UTC 24 |
Sep 18 07:50:14 PM UTC 24 |
235375054 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1619731084 |
|
|
Sep 18 07:50:08 PM UTC 24 |
Sep 18 07:50:15 PM UTC 24 |
809977546 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_stress_all.3141656396 |
|
|
Sep 18 07:50:10 PM UTC 24 |
Sep 18 07:50:16 PM UTC 24 |
2143047373 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3023074651 |
|
|
Sep 18 07:50:13 PM UTC 24 |
Sep 18 07:50:16 PM UTC 24 |
1289247797 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_esc_clk_rst_malfunc.2243937200 |
|
|
Sep 18 07:50:14 PM UTC 24 |
Sep 18 07:50:17 PM UTC 24 |
39396064 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_glitch.2850392286 |
|
|
Sep 18 07:50:14 PM UTC 24 |
Sep 18 07:50:17 PM UTC 24 |
47885201 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_global_esc.2897609123 |
|
|
Sep 18 07:50:14 PM UTC 24 |
Sep 18 07:50:17 PM UTC 24 |
120934446 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_disable_rom_integrity_check.3119052230 |
|
|
Sep 18 07:50:14 PM UTC 24 |
Sep 18 07:50:18 PM UTC 24 |
64880313 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_aborted_low_power.3526720354 |
|
|
Sep 18 07:50:16 PM UTC 24 |
Sep 18 07:50:18 PM UTC 24 |
56827125 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_reset.3534026508 |
|
|
Sep 18 07:50:15 PM UTC 24 |
Sep 18 07:50:18 PM UTC 24 |
135297782 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_escalation_timeout.4257047609 |
|
|
Sep 18 07:50:14 PM UTC 24 |
Sep 18 07:50:18 PM UTC 24 |
114625064 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_wakeup_reset.1417352307 |
|
|
Sep 18 07:50:16 PM UTC 24 |
Sep 18 07:50:18 PM UTC 24 |
252557912 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_ctrl_config_regwen.3197808917 |
|
|
Sep 18 07:50:14 PM UTC 24 |
Sep 18 07:50:18 PM UTC 24 |
185896693 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_wakeup.3932738901 |
|
|
Sep 18 07:50:15 PM UTC 24 |
Sep 18 07:50:18 PM UTC 24 |
393460938 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_reset_invalid.436345403 |
|
|
Sep 18 07:50:15 PM UTC 24 |
Sep 18 07:50:18 PM UTC 24 |
104451516 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_stress_all.1068834945 |
|
|
Sep 18 07:50:07 PM UTC 24 |
Sep 18 07:50:18 PM UTC 24 |
2791884921 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_lowpower_wakeup_race.3223435153 |
|
|
Sep 18 07:50:15 PM UTC 24 |
Sep 18 07:50:18 PM UTC 24 |
427137725 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3393600787 |
|
|
Sep 18 07:50:13 PM UTC 24 |
Sep 18 07:50:19 PM UTC 24 |
807144514 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_smoke.51058077 |
|
|
Sep 18 07:50:15 PM UTC 24 |
Sep 18 07:50:20 PM UTC 24 |
56485200 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_rstmgr_intersig_mubi.1367446018 |
|
|
Sep 18 07:50:14 PM UTC 24 |
Sep 18 07:50:20 PM UTC 24 |
54483379 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_lowpower_invalid.2247174947 |
|
|
Sep 18 07:50:15 PM UTC 24 |
Sep 18 07:50:20 PM UTC 24 |
42194437 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1007576383 |
|
|
Sep 18 07:50:17 PM UTC 24 |
Sep 18 07:50:20 PM UTC 24 |
921412423 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1110530156 |
|
|
Sep 18 07:50:17 PM UTC 24 |
Sep 18 07:50:21 PM UTC 24 |
1324497597 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_stress_all.451985394 |
|
|
Sep 18 07:50:15 PM UTC 24 |
Sep 18 07:50:23 PM UTC 24 |
3077714343 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_smoke.1251859825 |
|
|
Sep 18 07:50:20 PM UTC 24 |
Sep 18 07:50:23 PM UTC 24 |
57201478 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_stress_all.3123191423 |
|
|
Sep 18 07:50:19 PM UTC 24 |
Sep 18 07:50:34 PM UTC 24 |
1744824351 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_reset.4209796305 |
|
|
Sep 18 07:50:21 PM UTC 24 |
Sep 18 07:50:23 PM UTC 24 |
70912327 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_rstmgr_intersig_mubi.3104297620 |
|
|
Sep 18 07:50:32 PM UTC 24 |
Sep 18 07:50:34 PM UTC 24 |
93422543 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_stress_all_with_rand_reset.2363065891 |
|
|
Sep 18 07:50:06 PM UTC 24 |
Sep 18 07:50:23 PM UTC 24 |
6960658372 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_esc_clk_rst_malfunc.3240744051 |
|
|
Sep 18 07:50:19 PM UTC 24 |
Sep 18 07:50:24 PM UTC 24 |
39950698 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_glitch.3715243628 |
|
|
Sep 18 07:50:19 PM UTC 24 |
Sep 18 07:50:24 PM UTC 24 |
36225809 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_aborted_low_power.2847043919 |
|
|
Sep 18 07:50:21 PM UTC 24 |
Sep 18 07:50:24 PM UTC 24 |
120644872 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_global_esc.3077552334 |
|
|
Sep 18 07:50:19 PM UTC 24 |
Sep 18 07:50:24 PM UTC 24 |
27690026 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_wakeup.359359672 |
|
|
Sep 18 07:50:21 PM UTC 24 |
Sep 18 07:50:24 PM UTC 24 |
149007284 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_ctrl_config_regwen.3424432767 |
|
|
Sep 18 07:50:19 PM UTC 24 |
Sep 18 07:50:24 PM UTC 24 |
219979079 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_disable_rom_integrity_check.4033366307 |
|
|
Sep 18 07:50:19 PM UTC 24 |
Sep 18 07:50:24 PM UTC 24 |
100787931 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_lowpower_wakeup_race.2090527027 |
|
|
Sep 18 07:50:21 PM UTC 24 |
Sep 18 07:50:24 PM UTC 24 |
248554449 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_escalation_timeout.1211420639 |
|
|
Sep 18 07:50:19 PM UTC 24 |
Sep 18 07:50:24 PM UTC 24 |
249490585 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_rstmgr_intersig_mubi.2702179081 |
|
|
Sep 18 07:50:19 PM UTC 24 |
Sep 18 07:50:24 PM UTC 24 |
52872879 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_lowpower_invalid.3455387756 |
|
|
Sep 18 07:50:19 PM UTC 24 |
Sep 18 07:50:24 PM UTC 24 |
47380563 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_reset_invalid.3174188487 |
|
|
Sep 18 07:50:19 PM UTC 24 |
Sep 18 07:50:24 PM UTC 24 |
109465550 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_wakeup_reset.2724524368 |
|
|
Sep 18 07:50:21 PM UTC 24 |
Sep 18 07:50:24 PM UTC 24 |
262267688 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1505838159 |
|
|
Sep 18 07:50:22 PM UTC 24 |
Sep 18 07:50:26 PM UTC 24 |
1002000429 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.44963450 |
|
|
Sep 18 07:50:22 PM UTC 24 |
Sep 18 07:50:27 PM UTC 24 |
833135425 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_reset.4195547349 |
|
|
Sep 18 07:50:26 PM UTC 24 |
Sep 18 07:50:28 PM UTC 24 |
86401583 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_wakeup_reset.1377323413 |
|
|
Sep 18 07:50:26 PM UTC 24 |
Sep 18 07:50:28 PM UTC 24 |
108845057 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_aborted_low_power.1270686279 |
|
|
Sep 18 07:50:26 PM UTC 24 |
Sep 18 07:50:28 PM UTC 24 |
22444827 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_wakeup.3104430945 |
|
|
Sep 18 07:50:26 PM UTC 24 |
Sep 18 07:50:28 PM UTC 24 |
104072851 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_sec_cm_rstmgr_intersig_mubi.1818497955 |
|
|
Sep 18 07:50:23 PM UTC 24 |
Sep 18 07:50:28 PM UTC 24 |
59961074 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_lowpower_wakeup_race.1230647418 |
|
|
Sep 18 07:50:26 PM UTC 24 |
Sep 18 07:50:28 PM UTC 24 |
122040578 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_sec_cm_ctrl_config_regwen.2228645565 |
|
|
Sep 18 07:50:24 PM UTC 24 |
Sep 18 07:50:29 PM UTC 24 |
200160057 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_esc_clk_rst_malfunc.3718060574 |
|
|
Sep 18 07:50:24 PM UTC 24 |
Sep 18 07:50:29 PM UTC 24 |
31071781 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_global_esc.2034124712 |
|
|
Sep 18 07:50:24 PM UTC 24 |
Sep 18 07:50:29 PM UTC 24 |
65971714 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_escalation_timeout.3972395615 |
|
|
Sep 18 07:50:24 PM UTC 24 |
Sep 18 07:50:29 PM UTC 24 |
393359546 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_lowpower_invalid.4038978068 |
|
|
Sep 18 07:50:25 PM UTC 24 |
Sep 18 07:50:30 PM UTC 24 |
45145646 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_disable_rom_integrity_check.1987323442 |
|
|
Sep 18 07:50:25 PM UTC 24 |
Sep 18 07:50:30 PM UTC 24 |
65761477 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_smoke.3729080505 |
|
|
Sep 18 07:50:25 PM UTC 24 |
Sep 18 07:50:30 PM UTC 24 |
61640326 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_glitch.165726408 |
|
|
Sep 18 07:50:24 PM UTC 24 |
Sep 18 07:50:30 PM UTC 24 |
32370899 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_reset_invalid.3306066135 |
|
|
Sep 18 07:50:25 PM UTC 24 |
Sep 18 07:50:30 PM UTC 24 |
144881051 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_global_esc.2732622949 |
|
|
Sep 18 07:50:29 PM UTC 24 |
Sep 18 07:50:30 PM UTC 24 |
41915536 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_esc_clk_rst_malfunc.1849096829 |
|
|
Sep 18 07:50:28 PM UTC 24 |
Sep 18 07:50:30 PM UTC 24 |
29410456 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_sec_cm_ctrl_config_regwen.1847391471 |
|
|
Sep 18 07:50:29 PM UTC 24 |
Sep 18 07:50:31 PM UTC 24 |
497559134 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_sec_cm_rstmgr_intersig_mubi.1017786306 |
|
|
Sep 18 07:50:28 PM UTC 24 |
Sep 18 07:50:31 PM UTC 24 |
51238895 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.489650810 |
|
|
Sep 18 07:50:27 PM UTC 24 |
Sep 18 07:50:31 PM UTC 24 |
1234442143 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_stress_all_with_rand_reset.4188011161 |
|
|
Sep 18 07:50:15 PM UTC 24 |
Sep 18 07:50:31 PM UTC 24 |
3628341172 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_glitch.585068083 |
|
|
Sep 18 07:50:30 PM UTC 24 |
Sep 18 07:50:32 PM UTC 24 |
27629006 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_disable_rom_integrity_check.1241357532 |
|
|
Sep 18 07:50:30 PM UTC 24 |
Sep 18 07:50:32 PM UTC 24 |
64954916 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_reset_invalid.502809771 |
|
|
Sep 18 07:50:30 PM UTC 24 |
Sep 18 07:50:32 PM UTC 24 |
179541224 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_escalation_timeout.334209699 |
|
|
Sep 18 07:50:30 PM UTC 24 |
Sep 18 07:50:32 PM UTC 24 |
378669018 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2059767511 |
|
|
Sep 18 07:50:27 PM UTC 24 |
Sep 18 07:50:32 PM UTC 24 |
925014834 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_lowpower_invalid.862339189 |
|
|
Sep 18 07:50:30 PM UTC 24 |
Sep 18 07:50:33 PM UTC 24 |
43485358 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_smoke.486011078 |
|
|
Sep 18 07:50:31 PM UTC 24 |
Sep 18 07:50:33 PM UTC 24 |
31611040 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_lowpower_wakeup_race.1230200978 |
|
|
Sep 18 07:50:31 PM UTC 24 |
Sep 18 07:50:33 PM UTC 24 |
374797504 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_aborted_low_power.1347377510 |
|
|
Sep 18 07:50:32 PM UTC 24 |
Sep 18 07:50:34 PM UTC 24 |
29923800 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_wakeup.3935580337 |
|
|
Sep 18 07:50:31 PM UTC 24 |
Sep 18 07:50:34 PM UTC 24 |
133116882 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_reset.4267420769 |
|
|
Sep 18 07:50:31 PM UTC 24 |
Sep 18 07:50:34 PM UTC 24 |
72153169 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_wakeup_reset.513185533 |
|
|
Sep 18 07:50:31 PM UTC 24 |
Sep 18 07:50:34 PM UTC 24 |
443647068 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.818334071 |
|
|
Sep 18 07:50:32 PM UTC 24 |
Sep 18 07:50:35 PM UTC 24 |
1972435692 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_global_esc.2599627865 |
|
|
Sep 18 07:50:33 PM UTC 24 |
Sep 18 07:50:35 PM UTC 24 |
70728004 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_glitch.869220097 |
|
|
Sep 18 07:50:33 PM UTC 24 |
Sep 18 07:50:35 PM UTC 24 |
49961056 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_esc_clk_rst_malfunc.1075195009 |
|
|
Sep 18 07:50:33 PM UTC 24 |
Sep 18 07:50:35 PM UTC 24 |
30812722 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_ctrl_config_regwen.3200323657 |
|
|
Sep 18 07:50:33 PM UTC 24 |
Sep 18 07:50:35 PM UTC 24 |
267063903 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_escalation_timeout.2104506054 |
|
|
Sep 18 07:50:33 PM UTC 24 |
Sep 18 07:50:35 PM UTC 24 |
405910311 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_disable_rom_integrity_check.228108601 |
|
|
Sep 18 07:50:33 PM UTC 24 |
Sep 18 07:50:35 PM UTC 24 |
70509773 ps |
| T66 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_stress_all_with_rand_reset.2948584526 |
|
|
Sep 18 07:50:10 PM UTC 24 |
Sep 18 07:50:35 PM UTC 24 |
5073730748 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3800803309 |
|
|
Sep 18 07:50:32 PM UTC 24 |
Sep 18 07:50:36 PM UTC 24 |
995216522 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_stress_all_with_rand_reset.2702802548 |
|
|
Sep 18 07:50:19 PM UTC 24 |
Sep 18 07:50:36 PM UTC 24 |
1493624264 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_stress_all.2810823728 |
|
|
Sep 18 07:50:25 PM UTC 24 |
Sep 18 07:50:37 PM UTC 24 |
2382110756 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_smoke.1502479797 |
|
|
Sep 18 07:50:35 PM UTC 24 |
Sep 18 07:50:38 PM UTC 24 |
67330259 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_reset.1503966225 |
|
|
Sep 18 07:50:35 PM UTC 24 |
Sep 18 07:50:38 PM UTC 24 |
63707596 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_wakeup.53683162 |
|
|
Sep 18 07:50:35 PM UTC 24 |
Sep 18 07:50:38 PM UTC 24 |
77082366 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_lowpower_wakeup_race.16252470 |
|
|
Sep 18 07:50:35 PM UTC 24 |
Sep 18 07:50:38 PM UTC 24 |
354825577 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_aborted_low_power.2800380840 |
|
|
Sep 18 07:50:37 PM UTC 24 |
Sep 18 07:50:38 PM UTC 24 |
24376551 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_wakeup_reset.3190311202 |
|
|
Sep 18 07:50:37 PM UTC 24 |
Sep 18 07:50:39 PM UTC 24 |
119020648 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_global_esc.1291406629 |
|
|
Sep 18 07:50:37 PM UTC 24 |
Sep 18 07:50:39 PM UTC 24 |
180666662 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_esc_clk_rst_malfunc.1238252754 |
|
|
Sep 18 07:50:37 PM UTC 24 |
Sep 18 07:50:39 PM UTC 24 |
37957619 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_stress_all_with_rand_reset.70688464 |
|
|
Sep 18 07:50:25 PM UTC 24 |
Sep 18 07:50:39 PM UTC 24 |
5441468968 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_rstmgr_intersig_mubi.2824039446 |
|
|
Sep 18 07:50:37 PM UTC 24 |
Sep 18 07:50:39 PM UTC 24 |
168659332 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.526093184 |
|
|
Sep 18 07:50:37 PM UTC 24 |
Sep 18 07:50:40 PM UTC 24 |
1118178508 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_stress_all.4032730794 |
|
|
Sep 18 07:50:35 PM UTC 24 |
Sep 18 07:50:41 PM UTC 24 |
5076808287 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1856875483 |
|
|
Sep 18 07:50:37 PM UTC 24 |
Sep 18 07:50:41 PM UTC 24 |
748902544 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_wakeup.1300658965 |
|
|
Sep 18 07:50:40 PM UTC 24 |
Sep 18 07:50:43 PM UTC 24 |
68138259 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_aborted_low_power.953925519 |
|
|
Sep 18 07:50:40 PM UTC 24 |
Sep 18 07:50:43 PM UTC 24 |
58629981 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_stress_all.4220844216 |
|
|
Sep 18 07:50:31 PM UTC 24 |
Sep 18 07:50:43 PM UTC 24 |
2281918288 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_disable_rom_integrity_check.406134286 |
|
|
Sep 18 07:50:38 PM UTC 24 |
Sep 18 07:50:43 PM UTC 24 |
75009315 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_lowpower_invalid.3365590793 |
|
|
Sep 18 07:50:38 PM UTC 24 |
Sep 18 07:50:43 PM UTC 24 |
72755041 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_glitch.3235094232 |
|
|
Sep 18 07:50:38 PM UTC 24 |
Sep 18 07:50:43 PM UTC 24 |
42997447 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_reset_invalid.1304692529 |
|
|
Sep 18 07:50:38 PM UTC 24 |
Sep 18 07:50:43 PM UTC 24 |
109816054 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_lowpower_invalid.3647010458 |
|
|
Sep 18 07:50:35 PM UTC 24 |
Sep 18 07:50:44 PM UTC 24 |
142217661 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_esc_clk_rst_malfunc.1570674459 |
|
|
Sep 18 07:50:42 PM UTC 24 |
Sep 18 07:50:44 PM UTC 24 |
32542031 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_reset_invalid.836667114 |
|
|
Sep 18 07:50:35 PM UTC 24 |
Sep 18 07:50:44 PM UTC 24 |
263807543 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_rstmgr_intersig_mubi.631219069 |
|
|
Sep 18 07:50:42 PM UTC 24 |
Sep 18 07:50:44 PM UTC 24 |
102755894 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1509671258 |
|
|
Sep 18 07:50:40 PM UTC 24 |
Sep 18 07:50:44 PM UTC 24 |
1319392219 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1078016999 |
|
|
Sep 18 07:50:41 PM UTC 24 |
Sep 18 07:50:45 PM UTC 24 |
858378405 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_smoke.1993603724 |
|
|
Sep 18 07:50:39 PM UTC 24 |
Sep 18 07:50:48 PM UTC 24 |
30435625 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_reset.613500577 |
|
|
Sep 18 07:50:40 PM UTC 24 |
Sep 18 07:50:48 PM UTC 24 |
62061865 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_ctrl_config_regwen.2780997191 |
|
|
Sep 18 07:50:43 PM UTC 24 |
Sep 18 07:50:48 PM UTC 24 |
69657259 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_lowpower_wakeup_race.400216418 |
|
|
Sep 18 07:50:40 PM UTC 24 |
Sep 18 07:50:49 PM UTC 24 |
31144891 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_wakeup_reset.1151563217 |
|
|
Sep 18 07:50:40 PM UTC 24 |
Sep 18 07:50:49 PM UTC 24 |
309631080 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_ctrl_config_regwen.2249706502 |
|
|
Sep 18 07:50:37 PM UTC 24 |
Sep 18 07:50:49 PM UTC 24 |
229051465 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_escalation_timeout.3114502546 |
|
|
Sep 18 07:50:37 PM UTC 24 |
Sep 18 07:50:49 PM UTC 24 |
110615749 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_global_esc.2669320228 |
|
|
Sep 18 07:50:44 PM UTC 24 |
Sep 18 07:50:49 PM UTC 24 |
82793680 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_glitch.1634677893 |
|
|
Sep 18 07:50:45 PM UTC 24 |
Sep 18 07:50:49 PM UTC 24 |
28463897 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_disable_rom_integrity_check.3675736838 |
|
|
Sep 18 07:50:45 PM UTC 24 |
Sep 18 07:50:50 PM UTC 24 |
80888287 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_lowpower_invalid.3240485615 |
|
|
Sep 18 07:50:45 PM UTC 24 |
Sep 18 07:50:50 PM UTC 24 |
41096721 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_reset_invalid.1989081629 |
|
|
Sep 18 07:50:45 PM UTC 24 |
Sep 18 07:50:50 PM UTC 24 |
166714961 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_stress_all.3501390379 |
|
|
Sep 18 07:50:39 PM UTC 24 |
Sep 18 07:50:51 PM UTC 24 |
2334520493 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_stress_all_with_rand_reset.1973656776 |
|
|
Sep 18 07:50:30 PM UTC 24 |
Sep 18 07:50:52 PM UTC 24 |
9071818740 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_stress_all_with_rand_reset.1995845939 |
|
|
Sep 18 07:50:35 PM UTC 24 |
Sep 18 07:50:52 PM UTC 24 |
5857868252 ps |
| T1003 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_stress_all.3379148490 |
|
|
Sep 18 07:50:45 PM UTC 24 |
Sep 18 07:50:52 PM UTC 24 |
1641418253 ps |
| T1004 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_stress_all_with_rand_reset.2176398466 |
|
|
Sep 18 07:50:45 PM UTC 24 |
Sep 18 07:50:53 PM UTC 24 |
3134817265 ps |
| T1005 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_stress_all_with_rand_reset.275743384 |
|
|
Sep 18 07:50:38 PM UTC 24 |
Sep 18 07:50:55 PM UTC 24 |
8823320370 ps |
| T52 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_intr_test.903247052 |
|
|
Sep 18 07:50:46 PM UTC 24 |
Sep 18 07:50:48 PM UTC 24 |
18596823 ps |
| T53 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.2659402791 |
|
|
Sep 18 07:50:46 PM UTC 24 |
Sep 18 07:50:48 PM UTC 24 |
22521238 ps |
| T46 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.3166231492 |
|
|
Sep 18 07:50:46 PM UTC 24 |
Sep 18 07:50:48 PM UTC 24 |
111853351 ps |
| T47 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_tl_errors.530401823 |
|
|
Sep 18 07:50:45 PM UTC 24 |
Sep 18 07:50:48 PM UTC 24 |
278803393 ps |
| T70 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_rw.2115690791 |
|
|
Sep 18 07:50:50 PM UTC 24 |
Sep 18 07:50:53 PM UTC 24 |
105373743 ps |
| T61 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.3635858731 |
|
|
Sep 18 07:50:50 PM UTC 24 |
Sep 18 07:50:53 PM UTC 24 |
49197887 ps |
| T168 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.2547186184 |
|
|
Sep 18 07:50:50 PM UTC 24 |
Sep 18 07:50:53 PM UTC 24 |
93019984 ps |
| T167 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.23947337 |
|
|
Sep 18 07:50:50 PM UTC 24 |
Sep 18 07:50:53 PM UTC 24 |
71544461 ps |
| T62 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.2075753830 |
|
|
Sep 18 07:50:50 PM UTC 24 |
Sep 18 07:50:55 PM UTC 24 |
132388646 ps |
| T169 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.974739727 |
|
|
Sep 18 07:50:53 PM UTC 24 |
Sep 18 07:50:58 PM UTC 24 |
71179438 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.254842583 |
|
|
Sep 18 07:50:53 PM UTC 24 |
Sep 18 07:50:58 PM UTC 24 |
29659333 ps |
| T109 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.2716599700 |
|
|
Sep 18 07:50:53 PM UTC 24 |
Sep 18 07:50:58 PM UTC 24 |
24731797 ps |
| T170 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.1602761738 |
|
|
Sep 18 07:50:56 PM UTC 24 |
Sep 18 07:50:59 PM UTC 24 |
224556610 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.3042644062 |
|
|
Sep 18 07:50:56 PM UTC 24 |
Sep 18 07:50:59 PM UTC 24 |
33958679 ps |
| T67 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_tl_errors.1208249806 |
|
|
Sep 18 07:50:53 PM UTC 24 |
Sep 18 07:50:59 PM UTC 24 |
89532456 ps |
| T68 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.4056066132 |
|
|
Sep 18 07:50:55 PM UTC 24 |
Sep 18 07:51:00 PM UTC 24 |
84989132 ps |
| T159 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_intr_test.3945974083 |
|
|
Sep 18 07:50:54 PM UTC 24 |
Sep 18 07:51:00 PM UTC 24 |
51539656 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_rw.1550680819 |
|
|
Sep 18 07:50:55 PM UTC 24 |
Sep 18 07:51:00 PM UTC 24 |
20617734 ps |
| T56 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.3322686047 |
|
|
Sep 18 07:50:54 PM UTC 24 |
Sep 18 07:51:00 PM UTC 24 |
349439281 ps |
| T121 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_rw.415232120 |
|
|
Sep 18 07:50:50 PM UTC 24 |
Sep 18 07:51:01 PM UTC 24 |
37178553 ps |
| T160 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_intr_test.589571963 |
|
|
Sep 18 07:50:50 PM UTC 24 |
Sep 18 07:51:01 PM UTC 24 |
46327290 ps |
| T122 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.2925239802 |
|
|
Sep 18 07:51:06 PM UTC 24 |
Sep 18 07:51:08 PM UTC 24 |
19141814 ps |
| T1006 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.1710210687 |
|
|
Sep 18 07:50:50 PM UTC 24 |
Sep 18 07:51:01 PM UTC 24 |
45583387 ps |
| T1007 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_rw.2762978694 |
|
|
Sep 18 07:50:52 PM UTC 24 |
Sep 18 07:51:01 PM UTC 24 |
63811140 ps |
| T1008 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.1462482004 |
|
|
Sep 18 07:50:50 PM UTC 24 |
Sep 18 07:51:01 PM UTC 24 |
24440785 ps |
| T1009 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.617325726 |
|
|
Sep 18 07:50:52 PM UTC 24 |
Sep 18 07:51:01 PM UTC 24 |
45154767 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.2204734587 |
|
|
Sep 18 07:50:50 PM UTC 24 |
Sep 18 07:51:01 PM UTC 24 |
142202216 ps |
| T123 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.3656974910 |
|
|
Sep 18 07:50:50 PM UTC 24 |
Sep 18 07:51:01 PM UTC 24 |
104990768 ps |
| T161 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_intr_test.2501594639 |
|
|
Sep 18 07:50:52 PM UTC 24 |
Sep 18 07:51:02 PM UTC 24 |
80530193 ps |
| T162 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_intr_test.1403841590 |
|
|
Sep 18 07:50:59 PM UTC 24 |
Sep 18 07:51:02 PM UTC 24 |
40768221 ps |
| T57 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.3546768599 |
|
|
Sep 18 07:50:50 PM UTC 24 |
Sep 18 07:51:02 PM UTC 24 |
102312247 ps |
| T124 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.1983909696 |
|
|
Sep 18 07:50:59 PM UTC 24 |
Sep 18 07:51:02 PM UTC 24 |
87952173 ps |
| T69 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_tl_errors.454858315 |
|
|
Sep 18 07:50:51 PM UTC 24 |
Sep 18 07:51:02 PM UTC 24 |
32951215 ps |
| T74 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_tl_errors.7013660 |
|
|
Sep 18 07:50:59 PM UTC 24 |
Sep 18 07:51:02 PM UTC 24 |
177282918 ps |
| T71 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.4252688942 |
|
|
Sep 18 07:50:51 PM UTC 24 |
Sep 18 07:51:02 PM UTC 24 |
679205361 ps |
| T1010 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.1783924279 |
|
|
Sep 18 07:51:00 PM UTC 24 |
Sep 18 07:51:03 PM UTC 24 |
30432892 ps |
| T1011 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.103701191 |
|
|
Sep 18 07:50:59 PM UTC 24 |
Sep 18 07:51:03 PM UTC 24 |
140952782 ps |
| T63 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_tl_errors.449061970 |
|
|
Sep 18 07:50:50 PM UTC 24 |
Sep 18 07:51:03 PM UTC 24 |
103974779 ps |
| T76 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.2860327344 |
|
|
Sep 18 07:50:59 PM UTC 24 |
Sep 18 07:51:03 PM UTC 24 |
65891675 ps |
| T1012 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.3943133207 |
|
|
Sep 18 07:50:52 PM UTC 24 |
Sep 18 07:51:03 PM UTC 24 |
332779318 ps |
| T1013 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_rw.708789597 |
|
|
Sep 18 07:51:00 PM UTC 24 |
Sep 18 07:51:03 PM UTC 24 |
22501130 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.939388493 |
|
|
Sep 18 07:51:00 PM UTC 24 |
Sep 18 07:51:03 PM UTC 24 |
60200580 ps |
| T1014 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.63018673 |
|
|
Sep 18 07:50:50 PM UTC 24 |
Sep 18 07:51:03 PM UTC 24 |
216598290 ps |
| T64 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.3262897246 |
|
|
Sep 18 07:51:02 PM UTC 24 |
Sep 18 07:51:04 PM UTC 24 |
349856208 ps |
| T125 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.2820314567 |
|
|
Sep 18 07:51:02 PM UTC 24 |
Sep 18 07:51:04 PM UTC 24 |
33201736 ps |
| T1015 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.4074002882 |
|
|
Sep 18 07:51:00 PM UTC 24 |
Sep 18 07:51:05 PM UTC 24 |
422786634 ps |
| T1016 |
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_tl_errors.3972950522 |
|
|
Sep 18 07:51:02 PM UTC 24 |
Sep 18 07:51:05 PM UTC 24 |
140574810 ps |