Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4648 |
1 |
|
|
T5 |
7 |
|
T6 |
8 |
|
T26 |
11 |
auto[1] |
14249 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T5 |
9 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8379 |
1 |
|
|
T5 |
7 |
|
T6 |
5 |
|
T26 |
10 |
auto[1] |
10518 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T5 |
9 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
9133 |
1 |
|
|
T3 |
1 |
|
T5 |
11 |
|
T6 |
5 |
auto[1] |
9764 |
1 |
|
|
T1 |
1 |
|
T5 |
5 |
|
T6 |
10 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1033 |
1 |
|
|
T5 |
1 |
|
T6 |
3 |
|
T26 |
3 |
auto[0] |
auto[0] |
auto[1] |
1059 |
1 |
|
|
T5 |
2 |
|
T6 |
2 |
|
T26 |
3 |
auto[0] |
auto[1] |
auto[0] |
3372 |
1 |
|
|
T5 |
3 |
|
T26 |
3 |
|
T14 |
13 |
auto[0] |
auto[1] |
auto[1] |
2915 |
1 |
|
|
T5 |
1 |
|
T26 |
1 |
|
T14 |
16 |
auto[1] |
auto[0] |
auto[0] |
1126 |
1 |
|
|
T5 |
3 |
|
T26 |
3 |
|
T34 |
1 |
auto[1] |
auto[0] |
auto[1] |
1430 |
1 |
|
|
T5 |
1 |
|
T6 |
3 |
|
T26 |
2 |
auto[1] |
auto[1] |
auto[0] |
3602 |
1 |
|
|
T3 |
1 |
|
T5 |
4 |
|
T6 |
2 |
auto[1] |
auto[1] |
auto[1] |
4360 |
1 |
|
|
T1 |
1 |
|
T5 |
1 |
|
T6 |
5 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4648 |
1 |
|
|
T5 |
7 |
|
T6 |
8 |
|
T26 |
11 |
auto[1] |
14249 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T5 |
9 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8550 |
1 |
|
|
T3 |
1 |
|
T5 |
7 |
|
T6 |
7 |
auto[1] |
10347 |
1 |
|
|
T1 |
1 |
|
T5 |
9 |
|
T6 |
8 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
9031 |
1 |
|
|
T1 |
1 |
|
T5 |
5 |
|
T6 |
7 |
auto[1] |
9866 |
1 |
|
|
T3 |
1 |
|
T5 |
11 |
|
T6 |
8 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1088 |
1 |
|
|
T5 |
1 |
|
T6 |
1 |
|
T26 |
3 |
auto[0] |
auto[0] |
auto[1] |
1054 |
1 |
|
|
T5 |
2 |
|
T6 |
4 |
|
T26 |
3 |
auto[0] |
auto[1] |
auto[0] |
3352 |
1 |
|
|
T5 |
1 |
|
T6 |
1 |
|
T26 |
1 |
auto[0] |
auto[1] |
auto[1] |
3056 |
1 |
|
|
T3 |
1 |
|
T5 |
3 |
|
T6 |
1 |
auto[1] |
auto[0] |
auto[0] |
1054 |
1 |
|
|
T5 |
1 |
|
T6 |
1 |
|
T34 |
1 |
auto[1] |
auto[0] |
auto[1] |
1452 |
1 |
|
|
T5 |
3 |
|
T6 |
2 |
|
T26 |
5 |
auto[1] |
auto[1] |
auto[0] |
3537 |
1 |
|
|
T1 |
1 |
|
T5 |
2 |
|
T6 |
4 |
auto[1] |
auto[1] |
auto[1] |
4304 |
1 |
|
|
T5 |
3 |
|
T6 |
1 |
|
T26 |
3 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4648 |
1 |
|
|
T5 |
7 |
|
T6 |
8 |
|
T26 |
11 |
auto[1] |
14249 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T5 |
9 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8472 |
1 |
|
|
T5 |
5 |
|
T6 |
10 |
|
T26 |
11 |
auto[1] |
10425 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T5 |
11 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8981 |
1 |
|
|
T3 |
1 |
|
T5 |
6 |
|
T6 |
8 |
auto[1] |
9916 |
1 |
|
|
T1 |
1 |
|
T5 |
10 |
|
T6 |
7 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1056 |
1 |
|
|
T5 |
1 |
|
T6 |
3 |
|
T26 |
3 |
auto[0] |
auto[0] |
auto[1] |
1088 |
1 |
|
|
T6 |
2 |
|
T26 |
4 |
|
T34 |
1 |
auto[0] |
auto[1] |
auto[0] |
3316 |
1 |
|
|
T6 |
3 |
|
T26 |
1 |
|
T14 |
10 |
auto[0] |
auto[1] |
auto[1] |
3012 |
1 |
|
|
T5 |
4 |
|
T6 |
2 |
|
T26 |
3 |
auto[1] |
auto[0] |
auto[0] |
1073 |
1 |
|
|
T5 |
3 |
|
T6 |
1 |
|
T26 |
2 |
auto[1] |
auto[0] |
auto[1] |
1431 |
1 |
|
|
T5 |
3 |
|
T6 |
2 |
|
T26 |
2 |
auto[1] |
auto[1] |
auto[0] |
3536 |
1 |
|
|
T3 |
1 |
|
T5 |
2 |
|
T6 |
1 |
auto[1] |
auto[1] |
auto[1] |
4385 |
1 |
|
|
T1 |
1 |
|
T5 |
3 |
|
T6 |
1 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4648 |
1 |
|
|
T5 |
7 |
|
T6 |
8 |
|
T26 |
11 |
auto[1] |
14249 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T5 |
9 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8450 |
1 |
|
|
T5 |
5 |
|
T6 |
7 |
|
T26 |
4 |
auto[1] |
10447 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T5 |
11 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
9010 |
1 |
|
|
T3 |
1 |
|
T5 |
8 |
|
T6 |
5 |
auto[1] |
9887 |
1 |
|
|
T1 |
1 |
|
T5 |
8 |
|
T6 |
10 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1080 |
1 |
|
|
T6 |
1 |
|
T26 |
1 |
|
T34 |
3 |
auto[0] |
auto[0] |
auto[1] |
1044 |
1 |
|
|
T5 |
2 |
|
T6 |
1 |
|
T26 |
1 |
auto[0] |
auto[1] |
auto[0] |
3265 |
1 |
|
|
T5 |
1 |
|
T6 |
2 |
|
T26 |
1 |
auto[0] |
auto[1] |
auto[1] |
3061 |
1 |
|
|
T5 |
2 |
|
T6 |
3 |
|
T26 |
1 |
auto[1] |
auto[0] |
auto[0] |
1060 |
1 |
|
|
T5 |
4 |
|
T6 |
2 |
|
T26 |
3 |
auto[1] |
auto[0] |
auto[1] |
1464 |
1 |
|
|
T5 |
1 |
|
T6 |
4 |
|
T26 |
6 |
auto[1] |
auto[1] |
auto[0] |
3605 |
1 |
|
|
T3 |
1 |
|
T5 |
3 |
|
T26 |
3 |
auto[1] |
auto[1] |
auto[1] |
4318 |
1 |
|
|
T1 |
1 |
|
T5 |
3 |
|
T6 |
2 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4648 |
1 |
|
|
T5 |
7 |
|
T6 |
8 |
|
T26 |
11 |
auto[1] |
14249 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T5 |
9 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8583 |
1 |
|
|
T5 |
10 |
|
T6 |
10 |
|
T26 |
6 |
auto[1] |
10314 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T5 |
6 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8928 |
1 |
|
|
T5 |
9 |
|
T6 |
9 |
|
T26 |
9 |
auto[1] |
9969 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T5 |
7 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1025 |
1 |
|
|
T5 |
3 |
|
T6 |
2 |
|
T26 |
3 |
auto[0] |
auto[0] |
auto[1] |
1127 |
1 |
|
|
T5 |
2 |
|
T6 |
3 |
|
T26 |
1 |
auto[0] |
auto[1] |
auto[0] |
3327 |
1 |
|
|
T5 |
4 |
|
T6 |
2 |
|
T14 |
15 |
auto[0] |
auto[1] |
auto[1] |
3104 |
1 |
|
|
T5 |
1 |
|
T6 |
3 |
|
T26 |
2 |
auto[1] |
auto[0] |
auto[0] |
1059 |
1 |
|
|
T5 |
1 |
|
T6 |
3 |
|
T26 |
3 |
auto[1] |
auto[0] |
auto[1] |
1437 |
1 |
|
|
T5 |
1 |
|
T26 |
4 |
|
T34 |
5 |
auto[1] |
auto[1] |
auto[0] |
3517 |
1 |
|
|
T5 |
1 |
|
T6 |
2 |
|
T26 |
3 |
auto[1] |
auto[1] |
auto[1] |
4301 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T5 |
3 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4648 |
1 |
|
|
T5 |
7 |
|
T6 |
8 |
|
T26 |
11 |
auto[1] |
14249 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T5 |
9 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8544 |
1 |
|
|
T5 |
5 |
|
T6 |
5 |
|
T26 |
7 |
auto[1] |
10353 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T5 |
11 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
9030 |
1 |
|
|
T1 |
1 |
|
T5 |
7 |
|
T6 |
6 |
auto[1] |
9867 |
1 |
|
|
T3 |
1 |
|
T5 |
9 |
|
T6 |
9 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1051 |
1 |
|
|
T5 |
1 |
|
T6 |
1 |
|
T26 |
1 |
auto[0] |
auto[0] |
auto[1] |
1068 |
1 |
|
|
T5 |
1 |
|
T6 |
2 |
|
T26 |
3 |
auto[0] |
auto[1] |
auto[0] |
3423 |
1 |
|
|
T5 |
2 |
|
T6 |
1 |
|
T26 |
3 |
auto[0] |
auto[1] |
auto[1] |
3002 |
1 |
|
|
T5 |
1 |
|
T6 |
1 |
|
T14 |
9 |
auto[1] |
auto[0] |
auto[0] |
1068 |
1 |
|
|
T5 |
2 |
|
T6 |
2 |
|
T26 |
3 |
auto[1] |
auto[0] |
auto[1] |
1461 |
1 |
|
|
T5 |
3 |
|
T6 |
3 |
|
T26 |
4 |
auto[1] |
auto[1] |
auto[0] |
3488 |
1 |
|
|
T1 |
1 |
|
T5 |
2 |
|
T6 |
2 |
auto[1] |
auto[1] |
auto[1] |
4336 |
1 |
|
|
T3 |
1 |
|
T5 |
4 |
|
T6 |
3 |