Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	358447	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

139899

1

T1

7

T2

14

T3

12

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	255999	1			T1	17		T2	58		T3	19
values[0x0]	120784	1			T1	9		T2	18		T3	5
values[0x1]	121563	1			T1	1		T2	20		T3	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	283629	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

214717

1

T1

12

T2

34

T3

15

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1638	1			T14	17		T31	5		T15	2
valid_sources[0x01]	2418	1			T2	4		T9	1		T13	3
valid_sources[0x02]	1773	1			T2	2		T28	6		T31	7
valid_sources[0x03]	1540	1			T1	1		T13	2		T31	1
valid_sources[0x04]	1589	1			T31	6		T32	1		T33	1
valid_sources[0x05]	1757	1			T2	1		T9	3		T31	5
valid_sources[0x06]	1406	1			T9	3		T28	3		T31	5
valid_sources[0x07]	1637	1			T26	3		T14	1		T28	2
valid_sources[0x08]	1623	1			T26	2		T28	1		T31	3
valid_sources[0x09]	1510	1			T1	3		T9	2		T14	5
valid_sources[0x0a]	1593	1			T1	2		T31	3		T35	1
valid_sources[0x0b]	1839	1			T9	2		T28	3		T31	3
valid_sources[0x0c]	1708	1			T2	1		T9	3		T13	1
valid_sources[0x0d]	2263	1			T26	2		T31	2		T33	1
valid_sources[0x0e]	1758	1			T9	1		T28	6		T31	4
valid_sources[0x0f]	2005	1			T10	1		T28	1		T33	1
valid_sources[0x10]	2571	1			T31	4		T33	1		T16	2
valid_sources[0x11]	1565	1			T13	4		T31	6		T16	1
valid_sources[0x12]	1525	1			T2	1		T9	9		T40	2
valid_sources[0x13]	1783	1			T2	1		T9	1		T31	12
valid_sources[0x14]	1569	1			T26	1		T31	3		T16	5
valid_sources[0x15]	2858	1			T26	9		T14	13		T13	1
valid_sources[0x16]	1558	1			T1	1		T13	1		T31	12
valid_sources[0x17]	2648	1			T26	5		T40	8		T13	3
valid_sources[0x18]	2450	1			T14	8		T31	1		T33	1
valid_sources[0x19]	1552	1			T9	1		T14	13		T33	1
valid_sources[0x1a]	1879	1			T9	1		T13	1		T31	6
valid_sources[0x1b]	2519	1			T4	16		T26	3		T13	1
valid_sources[0x1c]	1940	1			T2	5		T31	8		T32	2
valid_sources[0x1d]	1766	1			T7	1		T9	1		T31	4
valid_sources[0x1e]	1589	1			T1	1		T2	4		T9	1
valid_sources[0x1f]	1857	1			T9	2		T14	39		T28	4
valid_sources[0x20]	3077	1			T26	1		T13	3		T31	5
valid_sources[0x21]	2833	1			T2	2		T9	2		T26	5
valid_sources[0x22]	1663	1			T9	3		T13	1		T31	7
valid_sources[0x23]	1704	1			T9	4		T14	7		T31	11
valid_sources[0x24]	2569	1			T1	1		T14	3		T31	3
valid_sources[0x25]	1443	1			T1	1		T9	3		T26	2
valid_sources[0x26]	1641	1			T2	2		T4	4		T26	8
valid_sources[0x27]	1667	1			T31	1		T32	2		T16	2
valid_sources[0x28]	1617	1			T40	5		T14	17		T31	3
valid_sources[0x29]	3037	1			T13	1		T31	2		T33	1
valid_sources[0x2a]	2150	1			T28	1		T31	2		T15	2
valid_sources[0x2b]	1517	1			T26	3		T31	8		T15	1
valid_sources[0x2c]	1590	1			T26	1		T13	1		T31	1
valid_sources[0x2d]	1977	1			T2	1		T9	2		T13	1
valid_sources[0x2e]	2653	1			T13	1		T31	6		T33	2
valid_sources[0x2f]	1915	1			T9	3		T28	14		T16	4
valid_sources[0x30]	1977	1			T26	5		T31	6		T16	4
valid_sources[0x31]	1661	1			T14	1		T15	1		T16	1
valid_sources[0x32]	1448	1			T9	1		T26	10		T28	1
valid_sources[0x33]	1392	1			T1	2		T2	2		T9	1
valid_sources[0x34]	2766	1			T14	19		T28	10		T31	6
valid_sources[0x35]	2792	1			T31	4		T15	1		T16	1
valid_sources[0x36]	1627	1			T31	2		T15	2		T35	1
valid_sources[0x37]	1552	1			T1	2		T13	1		T31	18
valid_sources[0x38]	1778	1			T9	1		T26	8		T14	10
valid_sources[0x39]	1834	1			T34	53		T16	2		T82	1
valid_sources[0x3a]	2460	1			T9	5		T13	1		T31	10
valid_sources[0x3b]	1688	1			T9	1		T28	2		T15	1
valid_sources[0x3c]	1891	1			T9	1		T31	4		T33	1
valid_sources[0x3d]	1694	1			T26	9		T31	5		T32	1
valid_sources[0x3e]	2376	1			T2	1		T4	15		T26	15
valid_sources[0x3f]	1603	1			T9	2		T13	1		T33	1
valid_sources[0x40]	2484	1			T28	8		T31	4		T33	1
valid_sources[0x41]	3946	1			T20	11		T33	1		T15	3
valid_sources[0x42]	1478	1			T9	1		T14	14		T35	1
valid_sources[0x43]	2063	1			T13	1		T31	1		T16	3
valid_sources[0x44]	1718	1			T28	1		T31	2		T32	1
valid_sources[0x45]	1760	1			T2	1		T32	1		T33	1
valid_sources[0x46]	1685	1			T9	3		T28	2		T31	3
valid_sources[0x47]	1587	1			T2	1		T9	2		T14	1
valid_sources[0x48]	1689	1			T28	5		T31	4		T32	2
valid_sources[0x49]	1382	1			T2	1		T4	13		T14	11
valid_sources[0x4a]	1616	1			T9	1		T26	1		T31	8
valid_sources[0x4b]	1546	1			T31	4		T33	1		T16	4
valid_sources[0x4c]	1703	1			T9	2		T26	14		T14	47
valid_sources[0x4d]	1795	1			T2	3		T9	2		T28	5
valid_sources[0x4e]	1707	1			T9	2		T14	1		T31	7
valid_sources[0x4f]	1539	1			T26	1		T31	3		T33	1
valid_sources[0x50]	1968	1			T9	4		T32	1		T35	1
valid_sources[0x51]	3079	1			T2	1		T31	4		T32	2
valid_sources[0x52]	1615	1			T28	1		T31	3		T15	1
valid_sources[0x53]	2270	1			T14	3		T31	2		T15	2
valid_sources[0x54]	1599	1			T2	1		T9	3		T14	18
valid_sources[0x55]	1564	1			T31	4		T32	2		T33	1
valid_sources[0x56]	1769	1			T9	1		T26	2		T14	4
valid_sources[0x57]	3140	1			T4	1		T9	6		T14	8
valid_sources[0x58]	1808	1			T9	1		T14	13		T13	2
valid_sources[0x59]	1694	1			T28	2		T31	1		T32	1
valid_sources[0x5a]	1550	1			T31	2		T33	1		T15	1
valid_sources[0x5b]	1702	1			T2	1		T9	1		T31	1
valid_sources[0x5c]	3347	1			T9	1		T14	19		T13	1
valid_sources[0x5d]	1573	1			T9	1		T26	5		T33	1
valid_sources[0x5e]	1577	1			T31	2		T35	3		T16	5
valid_sources[0x5f]	2467	1			T2	1		T9	1		T28	2
valid_sources[0x60]	2918	1			T2	1		T14	33		T28	2
valid_sources[0x61]	1749	1			T9	5		T26	1		T14	4
valid_sources[0x62]	3704	1			T9	2		T33	1		T15	2
valid_sources[0x63]	1707	1			T9	4		T26	2		T14	24
valid_sources[0x64]	1898	1			T8	1		T9	1		T14	4
valid_sources[0x65]	1558	1			T4	14		T14	1		T31	3
valid_sources[0x66]	1634	1			T2	1		T9	1		T26	3
valid_sources[0x67]	1563	1			T9	1		T31	3		T33	1
valid_sources[0x68]	1834	1			T16	3		T39	2		T155	1
valid_sources[0x69]	1584	1			T9	3		T31	5		T16	4
valid_sources[0x6a]	1752	1			T1	1		T9	1		T13	1
valid_sources[0x6b]	1933	1			T9	4		T31	3		T32	1
valid_sources[0x6c]	3817	1			T4	23		T9	4		T28	4
valid_sources[0x6d]	3025	1			T28	3		T33	1		T16	1
valid_sources[0x6e]	1583	1			T2	3		T26	1		T13	1
valid_sources[0x6f]	1529	1			T4	5		T9	6		T13	1
valid_sources[0x70]	1790	1			T14	38		T28	14		T31	3
valid_sources[0x71]	1858	1			T26	4		T14	9		T28	1
valid_sources[0x72]	2465	1			T4	18		T26	19		T13	1
valid_sources[0x73]	1591	1			T9	3		T14	1		T31	18
valid_sources[0x74]	2650	1			T9	3		T26	6		T28	4
valid_sources[0x75]	1561	1			T2	1		T26	1		T14	2
valid_sources[0x76]	1777	1			T9	8		T31	5		T34	1
valid_sources[0x77]	1497	1			T26	2		T14	20		T28	3
valid_sources[0x78]	1716	1			T2	1		T31	2		T32	1
valid_sources[0x79]	2651	1			T2	1		T4	2		T9	1
valid_sources[0x7a]	1769	1			T28	4		T31	2		T15	1
valid_sources[0x7b]	1526	1			T4	34		T9	2		T13	1
valid_sources[0x7c]	2207	1			T28	7		T33	2		T16	7
valid_sources[0x7d]	1947	1			T9	1		T13	1		T31	2
valid_sources[0x7e]	1628	1			T9	4		T31	3		T16	1
valid_sources[0x7f]	1711	1			T9	3		T33	1		T16	5
valid_sources[0x80]	1731	1			T9	1		T13	1		T31	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

67865

1

T1

7

T2

8

T3

9

values[0x0]

all_enables

biggest_size

46090

1

T2

4

T3

2

T4

22

values[0x1]

all_enables

biggest_size

25944

1

T2

2

T3

1

T4

15