Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

32                      
33         1/1            always_comb reset_or_disable = !rst_slow_ni || disable_sva;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T2,T3
1	0	Covered	T77,T78,T79

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	16048811	4496	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	16048811	174092	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	16048811	6510225	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	16048811	174113	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	16048811	4496	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	16048811	174092	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	16048811	6510225	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	16048811	174113	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16048811	4496	0	0
T1	1250	1	0	0
T2	2599	0	0	0
T3	1122	1	0	0
T4	1534	0	0	0
T5	14137	0	0	0
T6	16546	0	0	0
T7	2508	0	0	0
T8	1269	0	0	0
T9	3527	0	0	0
T10	9691	0	0	0
T14	0	19	0	0
T16	0	1	0	0
T31	0	17	0	0
T32	0	2	0	0
T38	0	22	0	0
T40	0	1	0	0
T80	0	17	0	0
T81	0	1	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16048811	174092	0	0
T1	1250	13	0	0
T2	2599	0	0	0
T3	1122	10	0	0
T4	1534	0	0	0
T5	14137	0	0	0
T6	16546	0	0	0
T7	2508	0	0	0
T8	1269	0	0	0
T9	3527	0	0	0
T10	9691	0	0	0
T14	0	1223	0	0
T16	0	11	0	0
T31	0	1007	0	0
T32	0	96	0	0
T38	0	442	0	0
T40	0	12	0	0
T80	0	422	0	0
T81	0	15	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16048811	6510225	0	0
T1	1250	996	0	0
T2	2599	0	0	0
T3	1122	822	0	0
T4	1534	957	0	0
T5	14137	5724	0	0
T6	16546	7365	0	0
T7	2508	0	0	0
T8	1269	0	0	0
T9	3527	0	0	0
T10	9691	0	0	0
T14	0	23973	0	0
T26	0	4042	0	0
T31	0	25735	0	0
T32	0	1569	0	0
T40	0	915	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16048811	174113	0	0
T1	1250	13	0	0
T2	2599	0	0	0
T3	1122	10	0	0
T4	1534	0	0	0
T5	14137	0	0	0
T6	16546	0	0	0
T7	2508	0	0	0
T8	1269	0	0	0
T9	3527	0	0	0
T10	9691	0	0	0
T14	0	1223	0	0
T16	0	11	0	0
T31	0	1007	0	0
T32	0	96	0	0
T38	0	442	0	0
T40	0	12	0	0
T80	0	422	0	0
T81	0	15	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16048811	4496	0	0
T1	1250	1	0	0
T2	2599	0	0	0
T3	1122	1	0	0
T4	1534	0	0	0
T5	14137	0	0	0
T6	16546	0	0	0
T7	2508	0	0	0
T8	1269	0	0	0
T9	3527	0	0	0
T10	9691	0	0	0
T14	0	19	0	0
T16	0	1	0	0
T31	0	17	0	0
T32	0	2	0	0
T38	0	22	0	0
T40	0	1	0	0
T80	0	17	0	0
T81	0	1	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16048811	174092	0	0
T1	1250	13	0	0
T2	2599	0	0	0
T3	1122	10	0	0
T4	1534	0	0	0
T5	14137	0	0	0
T6	16546	0	0	0
T7	2508	0	0	0
T8	1269	0	0	0
T9	3527	0	0	0
T10	9691	0	0	0
T14	0	1223	0	0
T16	0	11	0	0
T31	0	1007	0	0
T32	0	96	0	0
T38	0	442	0	0
T40	0	12	0	0
T80	0	422	0	0
T81	0	15	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16048811	6510225	0	0
T1	1250	996	0	0
T2	2599	0	0	0
T3	1122	822	0	0
T4	1534	957	0	0
T5	14137	5724	0	0
T6	16546	7365	0	0
T7	2508	0	0	0
T8	1269	0	0	0
T9	3527	0	0	0
T10	9691	0	0	0
T14	0	23973	0	0
T26	0	4042	0	0
T31	0	25735	0	0
T32	0	1569	0	0
T40	0	915	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16048811	174113	0	0
T1	1250	13	0	0
T2	2599	0	0	0
T3	1122	10	0	0
T4	1534	0	0	0
T5	14137	0	0	0
T6	16546	0	0	0
T7	2508	0	0	0
T8	1269	0	0	0
T9	3527	0	0	0
T10	9691	0	0	0
T14	0	1223	0	0
T16	0	11	0	0
T31	0	1007	0	0
T32	0	96	0	0
T38	0	442	0	0
T40	0	12	0	0
T80	0	422	0	0
T81	0	15	0	0