Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	16610245	16753	0	0
intr_enable_rd_A	16610245	32062	0	0
reset_en_rd_A	16610245	1166	0	0
reset_en_regwen_rd_A	16610245	1088	0	0
wake_info_capture_dis_rd_A	16610245	1218	0	0
wakeup_en_rd_A	16610245	2091	0	0
wakeup_en_regwen_rd_A	16610245	1070	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16610245	16753	0	0
T23	222449	20	0	0
T24	154387	12	0	0
T25	131062	36	0	0
T48	0	42	0	0
T49	0	107	0	0
T51	0	17	0	0
T88	62007	0	0	0
T99	2506	0	0	0
T100	1396	0	0	0
T101	3265	0	0	0
T102	2935	0	0	0
T103	4015	0	0	0
T104	2519	0	0	0
T127	0	10	0	0
T128	0	35	0	0
T129	0	1	0	0
T130	0	6	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16610245	32062	0	0
T12	2019	0	0	0
T13	5419	0	0	0
T14	57740	94	0	0
T17	1490	0	0	0
T20	9268	0	0	0
T26	10004	40	0	0
T28	6660	0	0	0
T31	52716	0	0	0
T32	4375	0	0	0
T33	0	23	0	0
T40	1185	0	0	0
T59	0	76	0	0
T78	0	21	0	0
T80	0	191	0	0
T84	0	34	0	0
T106	0	46	0	0
T131	0	3	0	0
T132	0	14	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16610245	1166	0	0
T23	222449	20	0	0
T24	154387	0	0	0
T25	131062	0	0	0
T48	0	14	0	0
T85	0	25	0	0
T88	62007	0	0	0
T98	0	24	0	0
T99	2506	0	0	0
T100	1396	0	0	0
T101	3265	0	0	0
T102	2935	0	0	0
T103	4015	0	0	0
T104	2519	0	0	0
T128	0	16	0	0
T133	0	6	0	0
T134	0	1	0	0
T135	0	7	0	0
T136	0	8	0	0
T137	0	21	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16610245	1088	0	0
T23	222449	14	0	0
T24	154387	0	0	0
T25	131062	0	0	0
T48	0	13	0	0
T85	0	33	0	0
T88	62007	0	0	0
T98	0	3	0	0
T99	2506	0	0	0
T100	1396	0	0	0
T101	3265	0	0	0
T102	2935	0	0	0
T103	4015	0	0	0
T104	2519	0	0	0
T128	0	27	0	0
T133	0	1	0	0
T135	0	10	0	0
T136	0	3	0	0
T138	0	7	0	0
T139	0	16	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16610245	1218	0	0
T23	222449	11	0	0
T24	154387	0	0	0
T25	131062	0	0	0
T48	0	10	0	0
T85	0	27	0	0
T88	62007	0	0	0
T98	0	9	0	0
T99	2506	0	0	0
T100	1396	0	0	0
T101	3265	0	0	0
T102	2935	0	0	0
T103	4015	0	0	0
T104	2519	0	0	0
T128	0	23	0	0
T133	0	15	0	0
T134	0	1	0	0
T135	0	13	0	0
T136	0	4	0	0
T139	0	6	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16610245	2091	0	0
T23	222449	7	0	0
T24	154387	0	0	0
T25	131062	0	0	0
T48	0	26	0	0
T85	0	28	0	0
T88	62007	0	0	0
T98	0	19	0	0
T99	2506	0	0	0
T100	1396	0	0	0
T101	3265	0	0	0
T102	2935	0	0	0
T103	4015	0	0	0
T104	2519	0	0	0
T128	0	20	0	0
T133	0	21	0	0
T134	0	4	0	0
T135	0	20	0	0
T136	0	5	0	0
T139	0	3	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16610245	1070	0	0
T23	222449	7	0	0
T24	154387	0	0	0
T25	131062	0	0	0
T48	0	13	0	0
T85	0	31	0	0
T88	62007	0	0	0
T98	0	2	0	0
T99	2506	0	0	0
T100	1396	0	0	0
T101	3265	0	0	0
T102	2935	0	0	0
T103	4015	0	0	0
T104	2519	0	0	0
T128	0	28	0	0
T133	0	15	0	0
T134	0	3	0	0
T135	0	17	0	0
T136	0	9	0	0
T139	0	6	0	0