Line Coverage for Module :
pwrmgr_reg_top
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 140 | 140 | 100.00 |
| ALWAYS | 70 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 121 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 264 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 278 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 284 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 298 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 320 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 521 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 556 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 917 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1089 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1104 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1120 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1136 | 1 | 1 | 100.00 |
| ALWAYS | 1228 | 18 | 18 | 100.00 |
| CONT_ASSIGN | 1248 | 1 | 1 | 100.00 |
| ALWAYS | 1252 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1273 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1275 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1276 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1278 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1279 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1281 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1282 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1284 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1285 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1286 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1288 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1290 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1292 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1294 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1296 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1298 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1299 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1301 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1302 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1304 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1305 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1307 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1309 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1311 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1313 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1315 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1317 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1318 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1320 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1321 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1323 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1325 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1326 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1328 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1329 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1330 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1332 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1334 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1336 | 1 | 1 | 100.00 |
| ALWAYS | 1340 | 18 | 18 | 100.00 |
| ALWAYS | 1362 | 40 | 40 | 100.00 |
| CONT_ASSIGN | 1464 | 0 | 0 | |
| CONT_ASSIGN | 1472 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1473 | 1 | 1 | 100.00 |
69 always_ff @(posedge clk_lc_i or negedge rst_lc_ni) begin
70 1/1 if (!rst_lc_ni) begin
Tests: T1 T2 T3
71 1/1 err_q <= '0;
Tests: T1 T2 T3
72 1/1 end else if (intg_err || reg_we_err) begin
Tests: T1 T2 T3
73 1/1 err_q <= 1'b1;
Tests: T20 T21 T22
74 end
MISSING_ELSE
75 end
76
77 // integrity error output is permanent and should be used for alert generation
78 // register errors are transactional
79 1/1 assign intg_err_o = err_q | intg_err | reg_we_err;
Tests: T1 T2 T3
80
81 // outgoing integrity generation
82 tlul_pkg::tl_d2h_t tl_o_pre;
83 tlul_rsp_intg_gen #(
84 .EnableRspIntgGen(1),
85 .EnableDataIntgGen(1)
86 ) u_rsp_intg_gen (
87 .tl_i(tl_o_pre),
88 .tl_o(tl_o)
89 );
90
91 1/1 assign tl_reg_h2d = tl_i;
Tests: T1 T2 T3
92 1/1 assign tl_o_pre = tl_reg_d2h;
Tests: T1 T2 T3
93
94 tlul_adapter_reg #(
95 .RegAw(AW),
96 .RegDw(DW),
97 .EnableDataIntgGen(0)
98 ) u_reg_if (
99 .clk_i (clk_i),
100 .rst_ni (rst_ni),
101
102 .tl_i (tl_reg_h2d),
103 .tl_o (tl_reg_d2h),
104
105 .en_ifetch_i(prim_mubi_pkg::MuBi4False),
106 .intg_error_o(),
107
108 .we_o (reg_we),
109 .re_o (reg_re),
110 .addr_o (reg_addr),
111 .wdata_o (reg_wdata),
112 .be_o (reg_be),
113 .busy_i (reg_busy),
114 .rdata_i (reg_rdata),
115 .error_i (reg_error)
116 );
117
118 // cdc oversampling signals
119
120 1/1 assign reg_rdata = reg_rdata_next ;
Tests: T1 T2 T3
121 1/1 assign reg_error = addrmiss | wr_err | intg_err;
Tests: T23 T25 T48
122
123 // Define SW related signals
124 // Format: <reg>_<field>_{wd|we|qs}
125 // or <reg>_{wd|we|qs} if field == 1 or 0
126 logic intr_state_we;
127 logic intr_state_qs;
128 logic intr_state_wd;
129 logic intr_enable_we;
130 logic intr_enable_qs;
131 logic intr_enable_wd;
132 logic intr_test_we;
133 logic intr_test_wd;
134 logic alert_test_we;
135 logic alert_test_wd;
136 logic ctrl_cfg_regwen_re;
137 logic ctrl_cfg_regwen_qs;
138 logic control_we;
139 logic control_low_power_hint_qs;
140 logic control_low_power_hint_wd;
141 logic control_core_clk_en_qs;
142 logic control_core_clk_en_wd;
143 logic control_io_clk_en_qs;
144 logic control_io_clk_en_wd;
145 logic control_usb_clk_en_lp_qs;
146 logic control_usb_clk_en_lp_wd;
147 logic control_usb_clk_en_active_qs;
148 logic control_usb_clk_en_active_wd;
149 logic control_main_pd_n_qs;
150 logic control_main_pd_n_wd;
151 logic cfg_cdc_sync_we;
152 logic cfg_cdc_sync_qs;
153 logic cfg_cdc_sync_wd;
154 logic wakeup_en_regwen_we;
155 logic wakeup_en_regwen_qs;
156 logic wakeup_en_regwen_wd;
157 logic wakeup_en_we;
158 logic wakeup_en_en_0_qs;
159 logic wakeup_en_en_0_wd;
160 logic wakeup_en_en_1_qs;
161 logic wakeup_en_en_1_wd;
162 logic wakeup_en_en_2_qs;
163 logic wakeup_en_en_2_wd;
164 logic wakeup_en_en_3_qs;
165 logic wakeup_en_en_3_wd;
166 logic wakeup_en_en_4_qs;
167 logic wakeup_en_en_4_wd;
168 logic wakeup_en_en_5_qs;
169 logic wakeup_en_en_5_wd;
170 logic wake_status_val_0_qs;
171 logic wake_status_val_1_qs;
172 logic wake_status_val_2_qs;
173 logic wake_status_val_3_qs;
174 logic wake_status_val_4_qs;
175 logic wake_status_val_5_qs;
176 logic reset_en_regwen_we;
177 logic reset_en_regwen_qs;
178 logic reset_en_regwen_wd;
179 logic reset_en_we;
180 logic reset_en_en_0_qs;
181 logic reset_en_en_0_wd;
182 logic reset_en_en_1_qs;
183 logic reset_en_en_1_wd;
184 logic reset_status_val_0_qs;
185 logic reset_status_val_1_qs;
186 logic escalate_reset_status_qs;
187 logic wake_info_capture_dis_we;
188 logic wake_info_capture_dis_qs;
189 logic wake_info_capture_dis_wd;
190 logic wake_info_re;
191 logic wake_info_we;
192 logic [5:0] wake_info_reasons_qs;
193 logic [5:0] wake_info_reasons_wd;
194 logic wake_info_fall_through_qs;
195 logic wake_info_fall_through_wd;
196 logic wake_info_abort_qs;
197 logic wake_info_abort_wd;
198 logic fault_status_reg_intg_err_qs;
199 logic fault_status_esc_timeout_qs;
200 logic fault_status_main_pd_glitch_qs;
201 // Define register CDC handling.
202 // CDC handling is done on a per-reg instead of per-field boundary.
203
204 // Register instances
205 // R[intr_state]: V(False)
206 prim_subreg #(
207 .DW (1),
208 .SwAccess(prim_subreg_pkg::SwAccessW1C),
209 .RESVAL (1'h0),
210 .Mubi (1'b0)
211 ) u_intr_state (
212 .clk_i (clk_i),
213 .rst_ni (rst_ni),
214
215 // from register interface
216 .we (intr_state_we),
217 .wd (intr_state_wd),
218
219 // from internal hardware
220 .de (hw2reg.intr_state.de),
221 .d (hw2reg.intr_state.d),
222
223 // to internal hardware
224 .qe (),
225 .q (reg2hw.intr_state.q),
226 .ds (),
227
228 // to register interface (read)
229 .qs (intr_state_qs)
230 );
231
232
233 // R[intr_enable]: V(False)
234 prim_subreg #(
235 .DW (1),
236 .SwAccess(prim_subreg_pkg::SwAccessRW),
237 .RESVAL (1'h0),
238 .Mubi (1'b0)
239 ) u_intr_enable (
240 .clk_i (clk_i),
241 .rst_ni (rst_ni),
242
243 // from register interface
244 .we (intr_enable_we),
245 .wd (intr_enable_wd),
246
247 // from internal hardware
248 .de (1'b0),
249 .d ('0),
250
251 // to internal hardware
252 .qe (),
253 .q (reg2hw.intr_enable.q),
254 .ds (),
255
256 // to register interface (read)
257 .qs (intr_enable_qs)
258 );
259
260
261 // R[intr_test]: V(True)
262 logic intr_test_qe;
263 logic [0:0] intr_test_flds_we;
264 1/1 assign intr_test_qe = &intr_test_flds_we;
Tests: T51 T52 T53
265 prim_subreg_ext #(
266 .DW (1)
267 ) u_intr_test (
268 .re (1'b0),
269 .we (intr_test_we),
270 .wd (intr_test_wd),
271 .d ('0),
272 .qre (),
273 .qe (intr_test_flds_we[0]),
274 .q (reg2hw.intr_test.q),
275 .ds (),
276 .qs ()
277 );
278 1/1 assign reg2hw.intr_test.qe = intr_test_qe;
Tests: T51 T52 T53
279
280
281 // R[alert_test]: V(True)
282 logic alert_test_qe;
283 logic [0:0] alert_test_flds_we;
284 1/1 assign alert_test_qe = &alert_test_flds_we;
Tests: T54 T53 T55
285 prim_subreg_ext #(
286 .DW (1)
287 ) u_alert_test (
288 .re (1'b0),
289 .we (alert_test_we),
290 .wd (alert_test_wd),
291 .d ('0),
292 .qre (),
293 .qe (alert_test_flds_we[0]),
294 .q (reg2hw.alert_test.q),
295 .ds (),
296 .qs ()
297 );
298 1/1 assign reg2hw.alert_test.qe = alert_test_qe;
Tests: T54 T53 T55
299
300
301 // R[ctrl_cfg_regwen]: V(True)
302 prim_subreg_ext #(
303 .DW (1)
304 ) u_ctrl_cfg_regwen (
305 .re (ctrl_cfg_regwen_re),
306 .we (1'b0),
307 .wd ('0),
308 .d (hw2reg.ctrl_cfg_regwen.d),
309 .qre (),
310 .qe (),
311 .q (),
312 .ds (),
313 .qs (ctrl_cfg_regwen_qs)
314 );
315
316
317 // R[control]: V(False)
318 // Create REGWEN-gated WE signal
319 logic control_gated_we;
320 1/1 assign control_gated_we = control_we & ctrl_cfg_regwen_qs;
Tests: T1 T2 T3
321 // F[low_power_hint]: 0:0
322 prim_subreg #(
323 .DW (1),
324 .SwAccess(prim_subreg_pkg::SwAccessRW),
325 .RESVAL (1'h0),
326 .Mubi (1'b0)
327 ) u_control_low_power_hint (
328 .clk_i (clk_i),
329 .rst_ni (rst_ni),
330
331 // from register interface
332 .we (control_gated_we),
333 .wd (control_low_power_hint_wd),
334
335 // from internal hardware
336 .de (hw2reg.control.low_power_hint.de),
337 .d (hw2reg.control.low_power_hint.d),
338
339 // to internal hardware
340 .qe (),
341 .q (reg2hw.control.low_power_hint.q),
342 .ds (),
343
344 // to register interface (read)
345 .qs (control_low_power_hint_qs)
346 );
347
348 // F[core_clk_en]: 4:4
349 prim_subreg #(
350 .DW (1),
351 .SwAccess(prim_subreg_pkg::SwAccessRW),
352 .RESVAL (1'h0),
353 .Mubi (1'b0)
354 ) u_control_core_clk_en (
355 .clk_i (clk_i),
356 .rst_ni (rst_ni),
357
358 // from register interface
359 .we (control_gated_we),
360 .wd (control_core_clk_en_wd),
361
362 // from internal hardware
363 .de (1'b0),
364 .d ('0),
365
366 // to internal hardware
367 .qe (),
368 .q (reg2hw.control.core_clk_en.q),
369 .ds (),
370
371 // to register interface (read)
372 .qs (control_core_clk_en_qs)
373 );
374
375 // F[io_clk_en]: 5:5
376 prim_subreg #(
377 .DW (1),
378 .SwAccess(prim_subreg_pkg::SwAccessRW),
379 .RESVAL (1'h0),
380 .Mubi (1'b0)
381 ) u_control_io_clk_en (
382 .clk_i (clk_i),
383 .rst_ni (rst_ni),
384
385 // from register interface
386 .we (control_gated_we),
387 .wd (control_io_clk_en_wd),
388
389 // from internal hardware
390 .de (1'b0),
391 .d ('0),
392
393 // to internal hardware
394 .qe (),
395 .q (reg2hw.control.io_clk_en.q),
396 .ds (),
397
398 // to register interface (read)
399 .qs (control_io_clk_en_qs)
400 );
401
402 // F[usb_clk_en_lp]: 6:6
403 prim_subreg #(
404 .DW (1),
405 .SwAccess(prim_subreg_pkg::SwAccessRW),
406 .RESVAL (1'h0),
407 .Mubi (1'b0)
408 ) u_control_usb_clk_en_lp (
409 .clk_i (clk_i),
410 .rst_ni (rst_ni),
411
412 // from register interface
413 .we (control_gated_we),
414 .wd (control_usb_clk_en_lp_wd),
415
416 // from internal hardware
417 .de (1'b0),
418 .d ('0),
419
420 // to internal hardware
421 .qe (),
422 .q (reg2hw.control.usb_clk_en_lp.q),
423 .ds (),
424
425 // to register interface (read)
426 .qs (control_usb_clk_en_lp_qs)
427 );
428
429 // F[usb_clk_en_active]: 7:7
430 prim_subreg #(
431 .DW (1),
432 .SwAccess(prim_subreg_pkg::SwAccessRW),
433 .RESVAL (1'h1),
434 .Mubi (1'b0)
435 ) u_control_usb_clk_en_active (
436 .clk_i (clk_i),
437 .rst_ni (rst_ni),
438
439 // from register interface
440 .we (control_gated_we),
441 .wd (control_usb_clk_en_active_wd),
442
443 // from internal hardware
444 .de (1'b0),
445 .d ('0),
446
447 // to internal hardware
448 .qe (),
449 .q (reg2hw.control.usb_clk_en_active.q),
450 .ds (),
451
452 // to register interface (read)
453 .qs (control_usb_clk_en_active_qs)
454 );
455
456 // F[main_pd_n]: 8:8
457 prim_subreg #(
458 .DW (1),
459 .SwAccess(prim_subreg_pkg::SwAccessRW),
460 .RESVAL (1'h1),
461 .Mubi (1'b0)
462 ) u_control_main_pd_n (
463 .clk_i (clk_i),
464 .rst_ni (rst_ni),
465
466 // from register interface
467 .we (control_gated_we),
468 .wd (control_main_pd_n_wd),
469
470 // from internal hardware
471 .de (1'b0),
472 .d ('0),
473
474 // to internal hardware
475 .qe (),
476 .q (reg2hw.control.main_pd_n.q),
477 .ds (),
478
479 // to register interface (read)
480 .qs (control_main_pd_n_qs)
481 );
482
483
484 // R[cfg_cdc_sync]: V(False)
485 logic cfg_cdc_sync_qe;
486 logic [0:0] cfg_cdc_sync_flds_we;
487 prim_flop #(
488 .Width(1),
489 .ResetValue(0)
490 ) u_cfg_cdc_sync0_qe (
491 .clk_i(clk_i),
492 .rst_ni(rst_ni),
493 .d_i(&cfg_cdc_sync_flds_we),
494 .q_o(cfg_cdc_sync_qe)
495 );
496 prim_subreg #(
497 .DW (1),
498 .SwAccess(prim_subreg_pkg::SwAccessRW),
499 .RESVAL (1'h0),
500 .Mubi (1'b0)
501 ) u_cfg_cdc_sync (
502 .clk_i (clk_i),
503 .rst_ni (rst_ni),
504
505 // from register interface
506 .we (cfg_cdc_sync_we),
507 .wd (cfg_cdc_sync_wd),
508
509 // from internal hardware
510 .de (hw2reg.cfg_cdc_sync.de),
511 .d (hw2reg.cfg_cdc_sync.d),
512
513 // to internal hardware
514 .qe (cfg_cdc_sync_flds_we[0]),
515 .q (reg2hw.cfg_cdc_sync.q),
516 .ds (),
517
518 // to register interface (read)
519 .qs (cfg_cdc_sync_qs)
520 );
521 1/1 assign reg2hw.cfg_cdc_sync.qe = cfg_cdc_sync_qe;
Tests: T1 T2 T3
522
523
524 // R[wakeup_en_regwen]: V(False)
525 prim_subreg #(
526 .DW (1),
527 .SwAccess(prim_subreg_pkg::SwAccessW0C),
528 .RESVAL (1'h1),
529 .Mubi (1'b0)
530 ) u_wakeup_en_regwen (
531 .clk_i (clk_i),
532 .rst_ni (rst_ni),
533
534 // from register interface
535 .we (wakeup_en_regwen_we),
536 .wd (wakeup_en_regwen_wd),
537
538 // from internal hardware
539 .de (1'b0),
540 .d ('0),
541
542 // to internal hardware
543 .qe (),
544 .q (),
545 .ds (),
546
547 // to register interface (read)
548 .qs (wakeup_en_regwen_qs)
549 );
550
551
552 // Subregister 0 of Multireg wakeup_en
553 // R[wakeup_en]: V(False)
554 // Create REGWEN-gated WE signal
555 logic wakeup_en_gated_we;
556 1/1 assign wakeup_en_gated_we = wakeup_en_we & wakeup_en_regwen_qs;
Tests: T1 T2 T3
557 // F[en_0]: 0:0
558 prim_subreg #(
559 .DW (1),
560 .SwAccess(prim_subreg_pkg::SwAccessRW),
561 .RESVAL (1'h0),
562 .Mubi (1'b0)
563 ) u_wakeup_en_en_0 (
564 .clk_i (clk_i),
565 .rst_ni (rst_ni),
566
567 // from register interface
568 .we (wakeup_en_gated_we),
569 .wd (wakeup_en_en_0_wd),
570
571 // from internal hardware
572 .de (1'b0),
573 .d ('0),
574
575 // to internal hardware
576 .qe (),
577 .q (reg2hw.wakeup_en[0].q),
578 .ds (),
579
580 // to register interface (read)
581 .qs (wakeup_en_en_0_qs)
582 );
583
584 // F[en_1]: 1:1
585 prim_subreg #(
586 .DW (1),
587 .SwAccess(prim_subreg_pkg::SwAccessRW),
588 .RESVAL (1'h0),
589 .Mubi (1'b0)
590 ) u_wakeup_en_en_1 (
591 .clk_i (clk_i),
592 .rst_ni (rst_ni),
593
594 // from register interface
595 .we (wakeup_en_gated_we),
596 .wd (wakeup_en_en_1_wd),
597
598 // from internal hardware
599 .de (1'b0),
600 .d ('0),
601
602 // to internal hardware
603 .qe (),
604 .q (reg2hw.wakeup_en[1].q),
605 .ds (),
606
607 // to register interface (read)
608 .qs (wakeup_en_en_1_qs)
609 );
610
611 // F[en_2]: 2:2
612 prim_subreg #(
613 .DW (1),
614 .SwAccess(prim_subreg_pkg::SwAccessRW),
615 .RESVAL (1'h0),
616 .Mubi (1'b0)
617 ) u_wakeup_en_en_2 (
618 .clk_i (clk_i),
619 .rst_ni (rst_ni),
620
621 // from register interface
622 .we (wakeup_en_gated_we),
623 .wd (wakeup_en_en_2_wd),
624
625 // from internal hardware
626 .de (1'b0),
627 .d ('0),
628
629 // to internal hardware
630 .qe (),
631 .q (reg2hw.wakeup_en[2].q),
632 .ds (),
633
634 // to register interface (read)
635 .qs (wakeup_en_en_2_qs)
636 );
637
638 // F[en_3]: 3:3
639 prim_subreg #(
640 .DW (1),
641 .SwAccess(prim_subreg_pkg::SwAccessRW),
642 .RESVAL (1'h0),
643 .Mubi (1'b0)
644 ) u_wakeup_en_en_3 (
645 .clk_i (clk_i),
646 .rst_ni (rst_ni),
647
648 // from register interface
649 .we (wakeup_en_gated_we),
650 .wd (wakeup_en_en_3_wd),
651
652 // from internal hardware
653 .de (1'b0),
654 .d ('0),
655
656 // to internal hardware
657 .qe (),
658 .q (reg2hw.wakeup_en[3].q),
659 .ds (),
660
661 // to register interface (read)
662 .qs (wakeup_en_en_3_qs)
663 );
664
665 // F[en_4]: 4:4
666 prim_subreg #(
667 .DW (1),
668 .SwAccess(prim_subreg_pkg::SwAccessRW),
669 .RESVAL (1'h0),
670 .Mubi (1'b0)
671 ) u_wakeup_en_en_4 (
672 .clk_i (clk_i),
673 .rst_ni (rst_ni),
674
675 // from register interface
676 .we (wakeup_en_gated_we),
677 .wd (wakeup_en_en_4_wd),
678
679 // from internal hardware
680 .de (1'b0),
681 .d ('0),
682
683 // to internal hardware
684 .qe (),
685 .q (reg2hw.wakeup_en[4].q),
686 .ds (),
687
688 // to register interface (read)
689 .qs (wakeup_en_en_4_qs)
690 );
691
692 // F[en_5]: 5:5
693 prim_subreg #(
694 .DW (1),
695 .SwAccess(prim_subreg_pkg::SwAccessRW),
696 .RESVAL (1'h0),
697 .Mubi (1'b0)
698 ) u_wakeup_en_en_5 (
699 .clk_i (clk_i),
700 .rst_ni (rst_ni),
701
702 // from register interface
703 .we (wakeup_en_gated_we),
704 .wd (wakeup_en_en_5_wd),
705
706 // from internal hardware
707 .de (1'b0),
708 .d ('0),
709
710 // to internal hardware
711 .qe (),
712 .q (reg2hw.wakeup_en[5].q),
713 .ds (),
714
715 // to register interface (read)
716 .qs (wakeup_en_en_5_qs)
717 );
718
719
720 // Subregister 0 of Multireg wake_status
721 // R[wake_status]: V(False)
722 // F[val_0]: 0:0
723 prim_subreg #(
724 .DW (1),
725 .SwAccess(prim_subreg_pkg::SwAccessRO),
726 .RESVAL (1'h0),
727 .Mubi (1'b0)
728 ) u_wake_status_val_0 (
729 .clk_i (clk_i),
730 .rst_ni (rst_ni),
731
732 // from register interface
733 .we (1'b0),
734 .wd ('0),
735
736 // from internal hardware
737 .de (hw2reg.wake_status[0].de),
738 .d (hw2reg.wake_status[0].d),
739
740 // to internal hardware
741 .qe (),
742 .q (),
743 .ds (),
744
745 // to register interface (read)
746 .qs (wake_status_val_0_qs)
747 );
748
749 // F[val_1]: 1:1
750 prim_subreg #(
751 .DW (1),
752 .SwAccess(prim_subreg_pkg::SwAccessRO),
753 .RESVAL (1'h0),
754 .Mubi (1'b0)
755 ) u_wake_status_val_1 (
756 .clk_i (clk_i),
757 .rst_ni (rst_ni),
758
759 // from register interface
760 .we (1'b0),
761 .wd ('0),
762
763 // from internal hardware
764 .de (hw2reg.wake_status[1].de),
765 .d (hw2reg.wake_status[1].d),
766
767 // to internal hardware
768 .qe (),
769 .q (),
770 .ds (),
771
772 // to register interface (read)
773 .qs (wake_status_val_1_qs)
774 );
775
776 // F[val_2]: 2:2
777 prim_subreg #(
778 .DW (1),
779 .SwAccess(prim_subreg_pkg::SwAccessRO),
780 .RESVAL (1'h0),
781 .Mubi (1'b0)
782 ) u_wake_status_val_2 (
783 .clk_i (clk_i),
784 .rst_ni (rst_ni),
785
786 // from register interface
787 .we (1'b0),
788 .wd ('0),
789
790 // from internal hardware
791 .de (hw2reg.wake_status[2].de),
792 .d (hw2reg.wake_status[2].d),
793
794 // to internal hardware
795 .qe (),
796 .q (),
797 .ds (),
798
799 // to register interface (read)
800 .qs (wake_status_val_2_qs)
801 );
802
803 // F[val_3]: 3:3
804 prim_subreg #(
805 .DW (1),
806 .SwAccess(prim_subreg_pkg::SwAccessRO),
807 .RESVAL (1'h0),
808 .Mubi (1'b0)
809 ) u_wake_status_val_3 (
810 .clk_i (clk_i),
811 .rst_ni (rst_ni),
812
813 // from register interface
814 .we (1'b0),
815 .wd ('0),
816
817 // from internal hardware
818 .de (hw2reg.wake_status[3].de),
819 .d (hw2reg.wake_status[3].d),
820
821 // to internal hardware
822 .qe (),
823 .q (),
824 .ds (),
825
826 // to register interface (read)
827 .qs (wake_status_val_3_qs)
828 );
829
830 // F[val_4]: 4:4
831 prim_subreg #(
832 .DW (1),
833 .SwAccess(prim_subreg_pkg::SwAccessRO),
834 .RESVAL (1'h0),
835 .Mubi (1'b0)
836 ) u_wake_status_val_4 (
837 .clk_i (clk_i),
838 .rst_ni (rst_ni),
839
840 // from register interface
841 .we (1'b0),
842 .wd ('0),
843
844 // from internal hardware
845 .de (hw2reg.wake_status[4].de),
846 .d (hw2reg.wake_status[4].d),
847
848 // to internal hardware
849 .qe (),
850 .q (),
851 .ds (),
852
853 // to register interface (read)
854 .qs (wake_status_val_4_qs)
855 );
856
857 // F[val_5]: 5:5
858 prim_subreg #(
859 .DW (1),
860 .SwAccess(prim_subreg_pkg::SwAccessRO),
861 .RESVAL (1'h0),
862 .Mubi (1'b0)
863 ) u_wake_status_val_5 (
864 .clk_i (clk_i),
865 .rst_ni (rst_ni),
866
867 // from register interface
868 .we (1'b0),
869 .wd ('0),
870
871 // from internal hardware
872 .de (hw2reg.wake_status[5].de),
873 .d (hw2reg.wake_status[5].d),
874
875 // to internal hardware
876 .qe (),
877 .q (),
878 .ds (),
879
880 // to register interface (read)
881 .qs (wake_status_val_5_qs)
882 );
883
884
885 // R[reset_en_regwen]: V(False)
886 prim_subreg #(
887 .DW (1),
888 .SwAccess(prim_subreg_pkg::SwAccessW0C),
889 .RESVAL (1'h1),
890 .Mubi (1'b0)
891 ) u_reset_en_regwen (
892 .clk_i (clk_i),
893 .rst_ni (rst_ni),
894
895 // from register interface
896 .we (reset_en_regwen_we),
897 .wd (reset_en_regwen_wd),
898
899 // from internal hardware
900 .de (1'b0),
901 .d ('0),
902
903 // to internal hardware
904 .qe (),
905 .q (),
906 .ds (),
907
908 // to register interface (read)
909 .qs (reset_en_regwen_qs)
910 );
911
912
913 // Subregister 0 of Multireg reset_en
914 // R[reset_en]: V(False)
915 // Create REGWEN-gated WE signal
916 logic reset_en_gated_we;
917 1/1 assign reset_en_gated_we = reset_en_we & reset_en_regwen_qs;
Tests: T1 T2 T3
918 // F[en_0]: 0:0
919 prim_subreg #(
920 .DW (1),
921 .SwAccess(prim_subreg_pkg::SwAccessRW),
922 .RESVAL (1'h0),
923 .Mubi (1'b0)
924 ) u_reset_en_en_0 (
925 .clk_i (clk_i),
926 .rst_ni (rst_ni),
927
928 // from register interface
929 .we (reset_en_gated_we),
930 .wd (reset_en_en_0_wd),
931
932 // from internal hardware
933 .de (1'b0),
934 .d ('0),
935
936 // to internal hardware
937 .qe (),
938 .q (reg2hw.reset_en[0].q),
939 .ds (),
940
941 // to register interface (read)
942 .qs (reset_en_en_0_qs)
943 );
944
945 // F[en_1]: 1:1
946 prim_subreg #(
947 .DW (1),
948 .SwAccess(prim_subreg_pkg::SwAccessRW),
949 .RESVAL (1'h0),
950 .Mubi (1'b0)
951 ) u_reset_en_en_1 (
952 .clk_i (clk_i),
953 .rst_ni (rst_ni),
954
955 // from register interface
956 .we (reset_en_gated_we),
957 .wd (reset_en_en_1_wd),
958
959 // from internal hardware
960 .de (1'b0),
961 .d ('0),
962
963 // to internal hardware
964 .qe (),
965 .q (reg2hw.reset_en[1].q),
966 .ds (),
967
968 // to register interface (read)
969 .qs (reset_en_en_1_qs)
970 );
971
972
973 // Subregister 0 of Multireg reset_status
974 // R[reset_status]: V(False)
975 // F[val_0]: 0:0
976 prim_subreg #(
977 .DW (1),
978 .SwAccess(prim_subreg_pkg::SwAccessRO),
979 .RESVAL (1'h0),
980 .Mubi (1'b0)
981 ) u_reset_status_val_0 (
982 .clk_i (clk_i),
983 .rst_ni (rst_ni),
984
985 // from register interface
986 .we (1'b0),
987 .wd ('0),
988
989 // from internal hardware
990 .de (hw2reg.reset_status[0].de),
991 .d (hw2reg.reset_status[0].d),
992
993 // to internal hardware
994 .qe (),
995 .q (),
996 .ds (),
997
998 // to register interface (read)
999 .qs (reset_status_val_0_qs)
1000 );
1001
1002 // F[val_1]: 1:1
1003 prim_subreg #(
1004 .DW (1),
1005 .SwAccess(prim_subreg_pkg::SwAccessRO),
1006 .RESVAL (1'h0),
1007 .Mubi (1'b0)
1008 ) u_reset_status_val_1 (
1009 .clk_i (clk_i),
1010 .rst_ni (rst_ni),
1011
1012 // from register interface
1013 .we (1'b0),
1014 .wd ('0),
1015
1016 // from internal hardware
1017 .de (hw2reg.reset_status[1].de),
1018 .d (hw2reg.reset_status[1].d),
1019
1020 // to internal hardware
1021 .qe (),
1022 .q (),
1023 .ds (),
1024
1025 // to register interface (read)
1026 .qs (reset_status_val_1_qs)
1027 );
1028
1029
1030 // R[escalate_reset_status]: V(False)
1031 prim_subreg #(
1032 .DW (1),
1033 .SwAccess(prim_subreg_pkg::SwAccessRO),
1034 .RESVAL (1'h0),
1035 .Mubi (1'b0)
1036 ) u_escalate_reset_status (
1037 .clk_i (clk_i),
1038 .rst_ni (rst_ni),
1039
1040 // from register interface
1041 .we (1'b0),
1042 .wd ('0),
1043
1044 // from internal hardware
1045 .de (hw2reg.escalate_reset_status.de),
1046 .d (hw2reg.escalate_reset_status.d),
1047
1048 // to internal hardware
1049 .qe (),
1050 .q (),
1051 .ds (),
1052
1053 // to register interface (read)
1054 .qs (escalate_reset_status_qs)
1055 );
1056
1057
1058 // R[wake_info_capture_dis]: V(False)
1059 prim_subreg #(
1060 .DW (1),
1061 .SwAccess(prim_subreg_pkg::SwAccessRW),
1062 .RESVAL (1'h0),
1063 .Mubi (1'b0)
1064 ) u_wake_info_capture_dis (
1065 .clk_i (clk_i),
1066 .rst_ni (rst_ni),
1067
1068 // from register interface
1069 .we (wake_info_capture_dis_we),
1070 .wd (wake_info_capture_dis_wd),
1071
1072 // from internal hardware
1073 .de (1'b0),
1074 .d ('0),
1075
1076 // to internal hardware
1077 .qe (),
1078 .q (reg2hw.wake_info_capture_dis.q),
1079 .ds (),
1080
1081 // to register interface (read)
1082 .qs (wake_info_capture_dis_qs)
1083 );
1084
1085
1086 // R[wake_info]: V(True)
1087 logic wake_info_qe;
1088 logic [2:0] wake_info_flds_we;
1089 1/1 assign wake_info_qe = &wake_info_flds_we;
Tests: T1 T2 T3
1090 // F[reasons]: 5:0
1091 prim_subreg_ext #(
1092 .DW (6)
1093 ) u_wake_info_reasons (
1094 .re (wake_info_re),
1095 .we (wake_info_we),
1096 .wd (wake_info_reasons_wd),
1097 .d (hw2reg.wake_info.reasons.d),
1098 .qre (),
1099 .qe (wake_info_flds_we[0]),
1100 .q (reg2hw.wake_info.reasons.q),
1101 .ds (),
1102 .qs (wake_info_reasons_qs)
1103 );
1104 1/1 assign reg2hw.wake_info.reasons.qe = wake_info_qe;
Tests: T1 T2 T3
1105
1106 // F[fall_through]: 6:6
1107 prim_subreg_ext #(
1108 .DW (1)
1109 ) u_wake_info_fall_through (
1110 .re (wake_info_re),
1111 .we (wake_info_we),
1112 .wd (wake_info_fall_through_wd),
1113 .d (hw2reg.wake_info.fall_through.d),
1114 .qre (),
1115 .qe (wake_info_flds_we[1]),
1116 .q (reg2hw.wake_info.fall_through.q),
1117 .ds (),
1118 .qs (wake_info_fall_through_qs)
1119 );
1120 1/1 assign reg2hw.wake_info.fall_through.qe = wake_info_qe;
Tests: T1 T2 T3
1121
1122 // F[abort]: 7:7
1123 prim_subreg_ext #(
1124 .DW (1)
1125 ) u_wake_info_abort (
1126 .re (wake_info_re),
1127 .we (wake_info_we),
1128 .wd (wake_info_abort_wd),
1129 .d (hw2reg.wake_info.abort.d),
1130 .qre (),
1131 .qe (wake_info_flds_we[2]),
1132 .q (reg2hw.wake_info.abort.q),
1133 .ds (),
1134 .qs (wake_info_abort_qs)
1135 );
1136 1/1 assign reg2hw.wake_info.abort.qe = wake_info_qe;
Tests: T1 T2 T3
1137
1138
1139 // R[fault_status]: V(False)
1140 // F[reg_intg_err]: 0:0
1141 prim_subreg #(
1142 .DW (1),
1143 .SwAccess(prim_subreg_pkg::SwAccessRO),
1144 .RESVAL (1'h0),
1145 .Mubi (1'b0)
1146 ) u_fault_status_reg_intg_err (
1147 // sync clock and reset required for this register
1148 .clk_i (clk_lc_i),
1149 .rst_ni (rst_lc_ni),
1150
1151 // from register interface
1152 .we (1'b0),
1153 .wd ('0),
1154
1155 // from internal hardware
1156 .de (hw2reg.fault_status.reg_intg_err.de),
1157 .d (hw2reg.fault_status.reg_intg_err.d),
1158
1159 // to internal hardware
1160 .qe (),
1161 .q (reg2hw.fault_status.reg_intg_err.q),
1162 .ds (),
1163
1164 // to register interface (read)
1165 .qs (fault_status_reg_intg_err_qs)
1166 );
1167
1168 // F[esc_timeout]: 1:1
1169 prim_subreg #(
1170 .DW (1),
1171 .SwAccess(prim_subreg_pkg::SwAccessRO),
1172 .RESVAL (1'h0),
1173 .Mubi (1'b0)
1174 ) u_fault_status_esc_timeout (
1175 // sync clock and reset required for this register
1176 .clk_i (clk_lc_i),
1177 .rst_ni (rst_lc_ni),
1178
1179 // from register interface
1180 .we (1'b0),
1181 .wd ('0),
1182
1183 // from internal hardware
1184 .de (hw2reg.fault_status.esc_timeout.de),
1185 .d (hw2reg.fault_status.esc_timeout.d),
1186
1187 // to internal hardware
1188 .qe (),
1189 .q (reg2hw.fault_status.esc_timeout.q),
1190 .ds (),
1191
1192 // to register interface (read)
1193 .qs (fault_status_esc_timeout_qs)
1194 );
1195
1196 // F[main_pd_glitch]: 2:2
1197 prim_subreg #(
1198 .DW (1),
1199 .SwAccess(prim_subreg_pkg::SwAccessRO),
1200 .RESVAL (1'h0),
1201 .Mubi (1'b0)
1202 ) u_fault_status_main_pd_glitch (
1203 // sync clock and reset required for this register
1204 .clk_i (clk_lc_i),
1205 .rst_ni (rst_lc_ni),
1206
1207 // from register interface
1208 .we (1'b0),
1209 .wd ('0),
1210
1211 // from internal hardware
1212 .de (hw2reg.fault_status.main_pd_glitch.de),
1213 .d (hw2reg.fault_status.main_pd_glitch.d),
1214
1215 // to internal hardware
1216 .qe (),
1217 .q (reg2hw.fault_status.main_pd_glitch.q),
1218 .ds (),
1219
1220 // to register interface (read)
1221 .qs (fault_status_main_pd_glitch_qs)
1222 );
1223
1224
1225
1226 logic [16:0] addr_hit;
1227 always_comb begin
1228 1/1 addr_hit = '0;
Tests: T1 T2 T3
1229 1/1 addr_hit[ 0] = (reg_addr == PWRMGR_INTR_STATE_OFFSET);
Tests: T1 T2 T3
1230 1/1 addr_hit[ 1] = (reg_addr == PWRMGR_INTR_ENABLE_OFFSET);
Tests: T1 T2 T3
1231 1/1 addr_hit[ 2] = (reg_addr == PWRMGR_INTR_TEST_OFFSET);
Tests: T1 T2 T3
1232 1/1 addr_hit[ 3] = (reg_addr == PWRMGR_ALERT_TEST_OFFSET);
Tests: T1 T2 T3
1233 1/1 addr_hit[ 4] = (reg_addr == PWRMGR_CTRL_CFG_REGWEN_OFFSET);
Tests: T1 T2 T3
1234 1/1 addr_hit[ 5] = (reg_addr == PWRMGR_CONTROL_OFFSET);
Tests: T1 T2 T3
1235 1/1 addr_hit[ 6] = (reg_addr == PWRMGR_CFG_CDC_SYNC_OFFSET);
Tests: T1 T2 T3
1236 1/1 addr_hit[ 7] = (reg_addr == PWRMGR_WAKEUP_EN_REGWEN_OFFSET);
Tests: T1 T2 T3
1237 1/1 addr_hit[ 8] = (reg_addr == PWRMGR_WAKEUP_EN_OFFSET);
Tests: T1 T2 T3
1238 1/1 addr_hit[ 9] = (reg_addr == PWRMGR_WAKE_STATUS_OFFSET);
Tests: T1 T2 T3
1239 1/1 addr_hit[10] = (reg_addr == PWRMGR_RESET_EN_REGWEN_OFFSET);
Tests: T1 T2 T3
1240 1/1 addr_hit[11] = (reg_addr == PWRMGR_RESET_EN_OFFSET);
Tests: T1 T2 T3
1241 1/1 addr_hit[12] = (reg_addr == PWRMGR_RESET_STATUS_OFFSET);
Tests: T1 T2 T3
1242 1/1 addr_hit[13] = (reg_addr == PWRMGR_ESCALATE_RESET_STATUS_OFFSET);
Tests: T1 T2 T3
1243 1/1 addr_hit[14] = (reg_addr == PWRMGR_WAKE_INFO_CAPTURE_DIS_OFFSET);
Tests: T1 T2 T3
1244 1/1 addr_hit[15] = (reg_addr == PWRMGR_WAKE_INFO_OFFSET);
Tests: T1 T2 T3
1245 1/1 addr_hit[16] = (reg_addr == PWRMGR_FAULT_STATUS_OFFSET);
Tests: T1 T2 T3
1246 end
1247
1248 1/1 assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
Tests: T1 T2 T3
1249
1250 // Check sub-word write is permitted
1251 always_comb begin
1252 1/1 wr_err = (reg_we &
Tests: T1 T2 T3
1253 ((addr_hit[ 0] & (|(PWRMGR_PERMIT[ 0] & ~reg_be))) |
1254 (addr_hit[ 1] & (|(PWRMGR_PERMIT[ 1] & ~reg_be))) |
1255 (addr_hit[ 2] & (|(PWRMGR_PERMIT[ 2] & ~reg_be))) |
1256 (addr_hit[ 3] & (|(PWRMGR_PERMIT[ 3] & ~reg_be))) |
1257 (addr_hit[ 4] & (|(PWRMGR_PERMIT[ 4] & ~reg_be))) |
1258 (addr_hit[ 5] & (|(PWRMGR_PERMIT[ 5] & ~reg_be))) |
1259 (addr_hit[ 6] & (|(PWRMGR_PERMIT[ 6] & ~reg_be))) |
1260 (addr_hit[ 7] & (|(PWRMGR_PERMIT[ 7] & ~reg_be))) |
1261 (addr_hit[ 8] & (|(PWRMGR_PERMIT[ 8] & ~reg_be))) |
1262 (addr_hit[ 9] & (|(PWRMGR_PERMIT[ 9] & ~reg_be))) |
1263 (addr_hit[10] & (|(PWRMGR_PERMIT[10] & ~reg_be))) |
1264 (addr_hit[11] & (|(PWRMGR_PERMIT[11] & ~reg_be))) |
1265 (addr_hit[12] & (|(PWRMGR_PERMIT[12] & ~reg_be))) |
1266 (addr_hit[13] & (|(PWRMGR_PERMIT[13] & ~reg_be))) |
1267 (addr_hit[14] & (|(PWRMGR_PERMIT[14] & ~reg_be))) |
1268 (addr_hit[15] & (|(PWRMGR_PERMIT[15] & ~reg_be))) |
1269 (addr_hit[16] & (|(PWRMGR_PERMIT[16] & ~reg_be)))));
1270 end
1271
1272 // Generate write-enables
1273 1/1 assign intr_state_we = addr_hit[0] & reg_we & !reg_error;
Tests: T1 T2 T3
1274
1275 1/1 assign intr_state_wd = reg_wdata[0];
Tests: T1 T2 T3
1276 1/1 assign intr_enable_we = addr_hit[1] & reg_we & !reg_error;
Tests: T1 T2 T3
1277
1278 1/1 assign intr_enable_wd = reg_wdata[0];
Tests: T1 T2 T3
1279 1/1 assign intr_test_we = addr_hit[2] & reg_we & !reg_error;
Tests: T1 T2 T3
1280
1281 1/1 assign intr_test_wd = reg_wdata[0];
Tests: T1 T2 T3
1282 1/1 assign alert_test_we = addr_hit[3] & reg_we & !reg_error;
Tests: T1 T2 T3
1283
1284 1/1 assign alert_test_wd = reg_wdata[0];
Tests: T1 T2 T3
1285 1/1 assign ctrl_cfg_regwen_re = addr_hit[4] & reg_re & !reg_error;
Tests: T1 T2 T3
1286 1/1 assign control_we = addr_hit[5] & reg_we & !reg_error;
Tests: T1 T2 T3
1287
1288 1/1 assign control_low_power_hint_wd = reg_wdata[0];
Tests: T1 T2 T3
1289
1290 1/1 assign control_core_clk_en_wd = reg_wdata[4];
Tests: T1 T2 T3
1291
1292 1/1 assign control_io_clk_en_wd = reg_wdata[5];
Tests: T1 T2 T3
1293
1294 1/1 assign control_usb_clk_en_lp_wd = reg_wdata[6];
Tests: T1 T2 T3
1295
1296 1/1 assign control_usb_clk_en_active_wd = reg_wdata[7];
Tests: T1 T2 T3
1297
1298 1/1 assign control_main_pd_n_wd = reg_wdata[8];
Tests: T1 T2 T3
1299 1/1 assign cfg_cdc_sync_we = addr_hit[6] & reg_we & !reg_error;
Tests: T1 T2 T3
1300
1301 1/1 assign cfg_cdc_sync_wd = reg_wdata[0];
Tests: T1 T2 T3
1302 1/1 assign wakeup_en_regwen_we = addr_hit[7] & reg_we & !reg_error;
Tests: T1 T2 T3
1303
1304 1/1 assign wakeup_en_regwen_wd = reg_wdata[0];
Tests: T1 T2 T3
1305 1/1 assign wakeup_en_we = addr_hit[8] & reg_we & !reg_error;
Tests: T1 T2 T3
1306
1307 1/1 assign wakeup_en_en_0_wd = reg_wdata[0];
Tests: T1 T2 T3
1308
1309 1/1 assign wakeup_en_en_1_wd = reg_wdata[1];
Tests: T1 T2 T3
1310
1311 1/1 assign wakeup_en_en_2_wd = reg_wdata[2];
Tests: T1 T2 T3
1312
1313 1/1 assign wakeup_en_en_3_wd = reg_wdata[3];
Tests: T1 T2 T3
1314
1315 1/1 assign wakeup_en_en_4_wd = reg_wdata[4];
Tests: T1 T2 T3
1316
1317 1/1 assign wakeup_en_en_5_wd = reg_wdata[5];
Tests: T1 T2 T3
1318 1/1 assign reset_en_regwen_we = addr_hit[10] & reg_we & !reg_error;
Tests: T1 T2 T3
1319
1320 1/1 assign reset_en_regwen_wd = reg_wdata[0];
Tests: T1 T2 T3
1321 1/1 assign reset_en_we = addr_hit[11] & reg_we & !reg_error;
Tests: T1 T2 T3
1322
1323 1/1 assign reset_en_en_0_wd = reg_wdata[0];
Tests: T1 T2 T3
1324
1325 1/1 assign reset_en_en_1_wd = reg_wdata[1];
Tests: T1 T2 T3
1326 1/1 assign wake_info_capture_dis_we = addr_hit[14] & reg_we & !reg_error;
Tests: T1 T2 T3
1327
1328 1/1 assign wake_info_capture_dis_wd = reg_wdata[0];
Tests: T1 T2 T3
1329 1/1 assign wake_info_re = addr_hit[15] & reg_re & !reg_error;
Tests: T1 T2 T3
1330 1/1 assign wake_info_we = addr_hit[15] & reg_we & !reg_error;
Tests: T1 T2 T3
1331
1332 1/1 assign wake_info_reasons_wd = reg_wdata[5:0];
Tests: T1 T2 T3
1333
1334 1/1 assign wake_info_fall_through_wd = reg_wdata[6];
Tests: T1 T2 T3
1335
1336 1/1 assign wake_info_abort_wd = reg_wdata[7];
Tests: T1 T2 T3
1337
1338 // Assign write-enables to checker logic vector.
1339 always_comb begin
1340 1/1 reg_we_check = '0;
Tests: T1 T2 T3
1341 1/1 reg_we_check[0] = intr_state_we;
Tests: T1 T2 T3
1342 1/1 reg_we_check[1] = intr_enable_we;
Tests: T1 T2 T3
1343 1/1 reg_we_check[2] = intr_test_we;
Tests: T1 T2 T3
1344 1/1 reg_we_check[3] = alert_test_we;
Tests: T1 T2 T3
1345 1/1 reg_we_check[4] = 1'b0;
Tests: T1 T2 T3
1346 1/1 reg_we_check[5] = control_gated_we;
Tests: T1 T2 T3
1347 1/1 reg_we_check[6] = cfg_cdc_sync_we;
Tests: T1 T2 T3
1348 1/1 reg_we_check[7] = wakeup_en_regwen_we;
Tests: T1 T2 T3
1349 1/1 reg_we_check[8] = wakeup_en_gated_we;
Tests: T1 T2 T3
1350 1/1 reg_we_check[9] = 1'b0;
Tests: T1 T2 T3
1351 1/1 reg_we_check[10] = reset_en_regwen_we;
Tests: T1 T2 T3
1352 1/1 reg_we_check[11] = reset_en_gated_we;
Tests: T1 T2 T3
1353 1/1 reg_we_check[12] = 1'b0;
Tests: T1 T2 T3
1354 1/1 reg_we_check[13] = 1'b0;
Tests: T1 T2 T3
1355 1/1 reg_we_check[14] = wake_info_capture_dis_we;
Tests: T1 T2 T3
1356 1/1 reg_we_check[15] = wake_info_we;
Tests: T1 T2 T3
1357 1/1 reg_we_check[16] = 1'b0;
Tests: T1 T2 T3
1358 end
1359
1360 // Read data return
1361 always_comb begin
1362 1/1 reg_rdata_next = '0;
Tests: T1 T2 T3
1363 1/1 unique case (1'b1)
Tests: T1 T2 T3
1364 addr_hit[0]: begin
1365 1/1 reg_rdata_next[0] = intr_state_qs;
Tests: T1 T2 T3
1366 end
1367
1368 addr_hit[1]: begin
1369 1/1 reg_rdata_next[0] = intr_enable_qs;
Tests: T1 T2 T3
1370 end
1371
1372 addr_hit[2]: begin
1373 1/1 reg_rdata_next[0] = '0;
Tests: T1 T2 T4
1374 end
1375
1376 addr_hit[3]: begin
1377 1/1 reg_rdata_next[0] = '0;
Tests: T1 T2 T3
1378 end
1379
1380 addr_hit[4]: begin
1381 1/1 reg_rdata_next[0] = ctrl_cfg_regwen_qs;
Tests: T1 T2 T3
1382 end
1383
1384 addr_hit[5]: begin
1385 1/1 reg_rdata_next[0] = control_low_power_hint_qs;
Tests: T1 T2 T3
1386 1/1 reg_rdata_next[4] = control_core_clk_en_qs;
Tests: T1 T2 T3
1387 1/1 reg_rdata_next[5] = control_io_clk_en_qs;
Tests: T1 T2 T3
1388 1/1 reg_rdata_next[6] = control_usb_clk_en_lp_qs;
Tests: T1 T2 T3
1389 1/1 reg_rdata_next[7] = control_usb_clk_en_active_qs;
Tests: T1 T2 T3
1390 1/1 reg_rdata_next[8] = control_main_pd_n_qs;
Tests: T1 T2 T3
1391 end
1392
1393 addr_hit[6]: begin
1394 1/1 reg_rdata_next[0] = cfg_cdc_sync_qs;
Tests: T1 T2 T3
1395 end
1396
1397 addr_hit[7]: begin
1398 1/1 reg_rdata_next[0] = wakeup_en_regwen_qs;
Tests: T1 T2 T4
1399 end
1400
1401 addr_hit[8]: begin
1402 1/1 reg_rdata_next[0] = wakeup_en_en_0_qs;
Tests: T1 T2 T3
1403 1/1 reg_rdata_next[1] = wakeup_en_en_1_qs;
Tests: T1 T2 T3
1404 1/1 reg_rdata_next[2] = wakeup_en_en_2_qs;
Tests: T1 T2 T3
1405 1/1 reg_rdata_next[3] = wakeup_en_en_3_qs;
Tests: T1 T2 T3
1406 1/1 reg_rdata_next[4] = wakeup_en_en_4_qs;
Tests: T1 T2 T3
1407 1/1 reg_rdata_next[5] = wakeup_en_en_5_qs;
Tests: T1 T2 T3
1408 end
1409
1410 addr_hit[9]: begin
1411 1/1 reg_rdata_next[0] = wake_status_val_0_qs;
Tests: T1 T2 T3
1412 1/1 reg_rdata_next[1] = wake_status_val_1_qs;
Tests: T1 T2 T3
1413 1/1 reg_rdata_next[2] = wake_status_val_2_qs;
Tests: T1 T2 T3
1414 1/1 reg_rdata_next[3] = wake_status_val_3_qs;
Tests: T1 T2 T3
1415 1/1 reg_rdata_next[4] = wake_status_val_4_qs;
Tests: T1 T2 T3
1416 1/1 reg_rdata_next[5] = wake_status_val_5_qs;
Tests: T1 T2 T3
1417 end
1418
1419 addr_hit[10]: begin
1420 1/1 reg_rdata_next[0] = reset_en_regwen_qs;
Tests: T2 T4 T5
1421 end
1422
1423 addr_hit[11]: begin
1424 1/1 reg_rdata_next[0] = reset_en_en_0_qs;
Tests: T1 T2 T3
1425 1/1 reg_rdata_next[1] = reset_en_en_1_qs;
Tests: T1 T2 T3
1426 end
1427
1428 addr_hit[12]: begin
1429 1/1 reg_rdata_next[0] = reset_status_val_0_qs;
Tests: T1 T2 T3
1430 1/1 reg_rdata_next[1] = reset_status_val_1_qs;
Tests: T1 T2 T3
1431 end
1432
1433 addr_hit[13]: begin
1434 1/1 reg_rdata_next[0] = escalate_reset_status_qs;
Tests: T2 T3 T4
1435 end
1436
1437 addr_hit[14]: begin
1438 1/1 reg_rdata_next[0] = wake_info_capture_dis_qs;
Tests: T1 T2 T3
1439 end
1440
1441 addr_hit[15]: begin
1442 1/1 reg_rdata_next[5:0] = wake_info_reasons_qs;
Tests: T1 T2 T3
1443 1/1 reg_rdata_next[6] = wake_info_fall_through_qs;
Tests: T1 T2 T3
1444 1/1 reg_rdata_next[7] = wake_info_abort_qs;
Tests: T1 T2 T3
1445 end
1446
1447 addr_hit[16]: begin
1448 1/1 reg_rdata_next[0] = fault_status_reg_intg_err_qs;
Tests: T2 T4 T5
1449 1/1 reg_rdata_next[1] = fault_status_esc_timeout_qs;
Tests: T2 T4 T5
1450 1/1 reg_rdata_next[2] = fault_status_main_pd_glitch_qs;
Tests: T2 T4 T5
1451 end
1452
1453 default: begin
1454 reg_rdata_next = '1;
1455 end
1456 endcase
1457 end
1458
1459 // shadow busy
1460 logic shadow_busy;
1461 assign shadow_busy = 1'b0;
1462
1463 // register busy
1464 unreachable assign reg_busy = shadow_busy;
1465
1466 // Unused signal tieoff
1467
1468 // wdata / byte enable are not always fully used
1469 // add a blanket unused statement to handle lint waivers
1470 logic unused_wdata;
1471 logic unused_be;
1472 1/1 assign unused_wdata = ^reg_wdata;
Tests: T1 T2 T3
1473 1/1 assign unused_be = ^reg_be;
Tests: T1 T2 T3
Cond Coverage for Module :
pwrmgr_reg_top
| Total | Covered | Percent |
|---|
| Conditions | 190 | 190 | 100.00 |
| Logical | 190 | 190 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 60
EXPRESSION (reg_we && ((!addrmiss)))
---1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T56,T47,T50 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 72
EXPRESSION (intg_err || reg_we_err)
----1--- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T20,T21,T22 |
| 1 | 0 | Covered | T50,T57,T58 |
LINE 79
EXPRESSION (err_q | intg_err | reg_we_err)
--1-- ----2--- -----3----
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 1 | Covered | T20,T21,T22 |
| 0 | 1 | 0 | Covered | T50,T57,T58 |
| 1 | 0 | 0 | Covered | T20,T21,T22 |
LINE 121
EXPRESSION (addrmiss | wr_err | intg_err)
----1--- ---2-- ----3---
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 1 | Covered | T50,T57,T58 |
| 0 | 1 | 0 | Covered | T23,T25,T48 |
| 1 | 0 | 0 | Covered | T23,T56,T46 |
LINE 320
EXPRESSION (control_we & ctrl_cfg_regwen_qs)
-----1---- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T59,T60,T61 |
| 1 | 1 | Covered | T1,T3,T4 |
LINE 556
EXPRESSION (wakeup_en_we & wakeup_en_regwen_qs)
------1----- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T53,T50,T62 |
| 1 | 1 | Covered | T1,T3,T4 |
LINE 917
EXPRESSION (reset_en_we & reset_en_regwen_qs)
-----1----- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T55,T63,T50 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 1229
EXPRESSION (reg_addr == pwrmgr_reg_pkg::PWRMGR_INTR_STATE_OFFSET)
---------------------------1--------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 1230
EXPRESSION (reg_addr == pwrmgr_reg_pkg::PWRMGR_INTR_ENABLE_OFFSET)
---------------------------1---------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 1231
EXPRESSION (reg_addr == pwrmgr_reg_pkg::PWRMGR_INTR_TEST_OFFSET)
--------------------------1--------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T4,T5 |
LINE 1232
EXPRESSION (reg_addr == pwrmgr_reg_pkg::PWRMGR_ALERT_TEST_OFFSET)
---------------------------1--------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T3,T4 |
LINE 1233
EXPRESSION (reg_addr == pwrmgr_reg_pkg::PWRMGR_CTRL_CFG_REGWEN_OFFSET)
-----------------------------1-----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T3,T4 |
LINE 1234
EXPRESSION (reg_addr == pwrmgr_reg_pkg::PWRMGR_CONTROL_OFFSET)
-------------------------1-------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T3,T4 |
LINE 1235
EXPRESSION (reg_addr == pwrmgr_reg_pkg::PWRMGR_CFG_CDC_SYNC_OFFSET)
----------------------------1---------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 1236
EXPRESSION (reg_addr == pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_REGWEN_OFFSET)
------------------------------1-----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T4,T5 |
LINE 1237
EXPRESSION (reg_addr == pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_OFFSET)
--------------------------1--------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T3,T4 |
LINE 1238
EXPRESSION (reg_addr == pwrmgr_reg_pkg::PWRMGR_WAKE_STATUS_OFFSET)
---------------------------1---------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T3,T4 |
LINE 1239
EXPRESSION (reg_addr == pwrmgr_reg_pkg::PWRMGR_RESET_EN_REGWEN_OFFSET)
-----------------------------1-----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T5,T6 |
LINE 1240
EXPRESSION (reg_addr == pwrmgr_reg_pkg::PWRMGR_RESET_EN_OFFSET)
--------------------------1-------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 1241
EXPRESSION (reg_addr == pwrmgr_reg_pkg::PWRMGR_RESET_STATUS_OFFSET)
----------------------------1---------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 1242
EXPRESSION (reg_addr == pwrmgr_reg_pkg::PWRMGR_ESCALATE_RESET_STATUS_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T4,T5 |
LINE 1243
EXPRESSION (reg_addr == pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_CAPTURE_DIS_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 1244
EXPRESSION (reg_addr == pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_OFFSET)
--------------------------1--------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 1245
EXPRESSION (reg_addr == pwrmgr_reg_pkg::PWRMGR_FAULT_STATUS_OFFSET)
----------------------------1---------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T5,T6 |
LINE 1248
EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
---------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 1248
SUB-EXPRESSION (reg_re || reg_we)
---1-- ---2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 1252
EXPRESSION
Number Term
1 reg_we &
2 ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1 & (~reg_be)))))))
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T23,T25,T48 |
LINE 1252
SUB-EXPRESSION
Number Term
1 (addr_hit[0] & ((|(4'b1 & (~reg_be))))) |
2 (addr_hit[1] & ((|(4'b1 & (~reg_be))))) |
3 (addr_hit[2] & ((|(4'b1 & (~reg_be))))) |
4 (addr_hit[3] & ((|(4'b1 & (~reg_be))))) |
5 (addr_hit[4] & ((|(4'b1 & (~reg_be))))) |
6 (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) |
7 (addr_hit[6] & ((|(4'b1 & (~reg_be))))) |
8 (addr_hit[7] & ((|(4'b1 & (~reg_be))))) |
9 (addr_hit[8] & ((|(4'b1 & (~reg_be))))) |
10 (addr_hit[9] & ((|(4'b1 & (~reg_be))))) |
11 (addr_hit[10] & ((|(4'b1 & (~reg_be))))) |
12 (addr_hit[11] & ((|(4'b1 & (~reg_be))))) |
13 (addr_hit[12] & ((|(4'b1 & (~reg_be))))) |
14 (addr_hit[13] & ((|(4'b1 & (~reg_be))))) |
15 (addr_hit[14] & ((|(4'b1 & (~reg_be))))) |
16 (addr_hit[15] & ((|(4'b1 & (~reg_be))))) |
17 (addr_hit[16] & ((|(4'b1 & (~reg_be))))))
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | -11- | -12- | -13- | -14- | -15- | -16- | -17- | Status | Tests |
|---|
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | Covered | T4,T5,T6 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | Covered | T3,T4,T5 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | Covered | T1,T4,T5 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | Covered | T3,T4,T5 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | Covered | T1,T3,T4 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T4,T5,T6 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T1,T4,T5 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T4,T5,T6 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T1,T4,T5 |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T3,T4,T5 |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T1,T3,T4 |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T1,T4,T5 |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T1,T4,T5 |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T3,T4,T5 |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T1,T3,T4 |
LINE 1252
SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T3,T4 |
LINE 1252
SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T3,T4,T5 |
LINE 1252
SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T4,T5,T6 |
| 1 | 1 | Covered | T1,T4,T5 |
LINE 1252
SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T3,T4 |
| 1 | 1 | Covered | T1,T4,T5 |
LINE 1252
SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T3,T4 |
| 1 | 1 | Covered | T1,T3,T4 |
LINE 1252
SUB-EXPRESSION (addr_hit[5] & ((|(4'b0011 & (~reg_be)))))
-----1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T3,T4 |
| 1 | 1 | Covered | T3,T4,T5 |
LINE 1252
SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 1252
SUB-EXPRESSION (addr_hit[7] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T4,T5,T26 |
| 1 | 1 | Covered | T1,T4,T5 |
LINE 1252
SUB-EXPRESSION (addr_hit[8] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T3,T4 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 1252
SUB-EXPRESSION (addr_hit[9] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T3,T4 |
| 1 | 1 | Covered | T1,T4,T5 |
LINE 1252
SUB-EXPRESSION (addr_hit[10] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T4,T5,T6 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 1252
SUB-EXPRESSION (addr_hit[11] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T3,T4 |
LINE 1252
SUB-EXPRESSION (addr_hit[12] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 1252
SUB-EXPRESSION (addr_hit[13] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T3,T4,T5 |
| 1 | 1 | Covered | T3,T4,T5 |
LINE 1252
SUB-EXPRESSION (addr_hit[14] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T4,T5 |
LINE 1252
SUB-EXPRESSION (addr_hit[15] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T3,T4,T5 |
LINE 1252
SUB-EXPRESSION (addr_hit[16] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T4,T5,T6 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 1273
EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T47,T64,T65 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 1276
EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T51,T50,T66 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 1279
EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T4,T5 |
| 1 | 1 | 0 | Covered | T51,T47,T67 |
| 1 | 1 | 1 | Covered | T52,T53,T68 |
LINE 1282
EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T3,T4 |
| 1 | 1 | 0 | Covered | T54,T47,T64 |
| 1 | 1 | 1 | Covered | T53,T55,T63 |
LINE 1285
EXPRESSION (addr_hit[4] & reg_re & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T3,T4 |
| 1 | 1 | 0 | Covered | T69,T70,T71 |
| 1 | 1 | 1 | Covered | T23,T24,T25 |
LINE 1286
EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T3,T4 |
| 1 | 1 | 0 | Covered | T47,T50,T66 |
| 1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 1299
EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T72,T73,T47 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 1302
EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T4,T5 |
| 1 | 1 | 0 | Covered | T56,T47,T67 |
| 1 | 1 | 1 | Covered | T53,T55,T63 |
LINE 1305
EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T3,T4 |
| 1 | 1 | 0 | Covered | T49,T47,T66 |
| 1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 1318
EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T4,T5 |
| 1 | 1 | 0 | Covered | T25,T51,T74 |
| 1 | 1 | 1 | Covered | T53,T55,T63 |
LINE 1321
EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T72,T47,T66 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 1326
EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T48,T47,T66 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 1329
EXPRESSION (addr_hit[15] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T50,T57,T69 |
| 1 | 1 | 1 | Covered | T2,T3,T5 |
LINE 1330
EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T47,T75,T76 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
pwrmgr_reg_top
| Line No. | Total | Covered | Percent |
| Branches |
|
23 |
23 |
100.00 |
| TERNARY |
1248 |
2 |
2 |
100.00 |
| IF |
70 |
3 |
3 |
100.00 |
| CASE |
1363 |
18 |
18 |
100.00 |
1248 assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
70 if (!rst_lc_ni) begin
-1-
71 err_q <= '0;
==>
72 end else if (intg_err || reg_we_err) begin
-2-
73 err_q <= 1'b1;
==>
74 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T20,T21,T22 |
| 0 |
0 |
Covered |
T1,T2,T3 |
1363 unique case (1'b1)
-1-
1364 addr_hit[0]: begin
1365 reg_rdata_next[0] = intr_state_qs;
==>
1366 end
1367
1368 addr_hit[1]: begin
1369 reg_rdata_next[0] = intr_enable_qs;
==>
1370 end
1371
1372 addr_hit[2]: begin
1373 reg_rdata_next[0] = '0;
==>
1374 end
1375
1376 addr_hit[3]: begin
1377 reg_rdata_next[0] = '0;
==>
1378 end
1379
1380 addr_hit[4]: begin
1381 reg_rdata_next[0] = ctrl_cfg_regwen_qs;
==>
1382 end
1383
1384 addr_hit[5]: begin
1385 reg_rdata_next[0] = control_low_power_hint_qs;
==>
1386 reg_rdata_next[4] = control_core_clk_en_qs;
1387 reg_rdata_next[5] = control_io_clk_en_qs;
1388 reg_rdata_next[6] = control_usb_clk_en_lp_qs;
1389 reg_rdata_next[7] = control_usb_clk_en_active_qs;
1390 reg_rdata_next[8] = control_main_pd_n_qs;
1391 end
1392
1393 addr_hit[6]: begin
1394 reg_rdata_next[0] = cfg_cdc_sync_qs;
==>
1395 end
1396
1397 addr_hit[7]: begin
1398 reg_rdata_next[0] = wakeup_en_regwen_qs;
==>
1399 end
1400
1401 addr_hit[8]: begin
1402 reg_rdata_next[0] = wakeup_en_en_0_qs;
==>
1403 reg_rdata_next[1] = wakeup_en_en_1_qs;
1404 reg_rdata_next[2] = wakeup_en_en_2_qs;
1405 reg_rdata_next[3] = wakeup_en_en_3_qs;
1406 reg_rdata_next[4] = wakeup_en_en_4_qs;
1407 reg_rdata_next[5] = wakeup_en_en_5_qs;
1408 end
1409
1410 addr_hit[9]: begin
1411 reg_rdata_next[0] = wake_status_val_0_qs;
==>
1412 reg_rdata_next[1] = wake_status_val_1_qs;
1413 reg_rdata_next[2] = wake_status_val_2_qs;
1414 reg_rdata_next[3] = wake_status_val_3_qs;
1415 reg_rdata_next[4] = wake_status_val_4_qs;
1416 reg_rdata_next[5] = wake_status_val_5_qs;
1417 end
1418
1419 addr_hit[10]: begin
1420 reg_rdata_next[0] = reset_en_regwen_qs;
==>
1421 end
1422
1423 addr_hit[11]: begin
1424 reg_rdata_next[0] = reset_en_en_0_qs;
==>
1425 reg_rdata_next[1] = reset_en_en_1_qs;
1426 end
1427
1428 addr_hit[12]: begin
1429 reg_rdata_next[0] = reset_status_val_0_qs;
==>
1430 reg_rdata_next[1] = reset_status_val_1_qs;
1431 end
1432
1433 addr_hit[13]: begin
1434 reg_rdata_next[0] = escalate_reset_status_qs;
==>
1435 end
1436
1437 addr_hit[14]: begin
1438 reg_rdata_next[0] = wake_info_capture_dis_qs;
==>
1439 end
1440
1441 addr_hit[15]: begin
1442 reg_rdata_next[5:0] = wake_info_reasons_qs;
==>
1443 reg_rdata_next[6] = wake_info_fall_through_qs;
1444 reg_rdata_next[7] = wake_info_abort_qs;
1445 end
1446
1447 addr_hit[16]: begin
1448 reg_rdata_next[0] = fault_status_reg_intg_err_qs;
==>
1449 reg_rdata_next[1] = fault_status_esc_timeout_qs;
1450 reg_rdata_next[2] = fault_status_main_pd_glitch_qs;
1451 end
1452
1453 default: begin
1454 reg_rdata_next = '1;
==>
Branches:
| -1- | Status | Tests |
| addr_hit[0] |
Covered |
T1,T2,T3 |
| addr_hit[1] |
Covered |
T1,T2,T3 |
| addr_hit[2] |
Covered |
T1,T2,T4 |
| addr_hit[3] |
Covered |
T1,T2,T3 |
| addr_hit[4] |
Covered |
T1,T2,T3 |
| addr_hit[5] |
Covered |
T1,T2,T3 |
| addr_hit[6] |
Covered |
T1,T2,T3 |
| addr_hit[7] |
Covered |
T1,T2,T4 |
| addr_hit[8] |
Covered |
T1,T2,T3 |
| addr_hit[9] |
Covered |
T1,T2,T3 |
| addr_hit[10] |
Covered |
T2,T4,T5 |
| addr_hit[11] |
Covered |
T1,T2,T3 |
| addr_hit[12] |
Covered |
T1,T2,T3 |
| addr_hit[13] |
Covered |
T2,T3,T4 |
| addr_hit[14] |
Covered |
T1,T2,T3 |
| addr_hit[15] |
Covered |
T1,T2,T3 |
| addr_hit[16] |
Covered |
T2,T4,T5 |
| default |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
pwrmgr_reg_top
Assertion Details
en2addrHit
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
16610245 |
486474 |
0 |
0 |
| T1 |
1250 |
27 |
0 |
0 |
| T2 |
2599 |
96 |
0 |
0 |
| T3 |
1122 |
30 |
0 |
0 |
| T4 |
1534 |
281 |
0 |
0 |
| T5 |
14137 |
254 |
0 |
0 |
| T6 |
16546 |
187 |
0 |
0 |
| T7 |
2508 |
1 |
0 |
0 |
| T8 |
1269 |
1 |
0 |
0 |
| T9 |
3527 |
244 |
0 |
0 |
| T10 |
9691 |
1 |
0 |
0 |
reAfterRv
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
16610245 |
486472 |
0 |
0 |
| T1 |
1250 |
27 |
0 |
0 |
| T2 |
2599 |
96 |
0 |
0 |
| T3 |
1122 |
30 |
0 |
0 |
| T4 |
1534 |
281 |
0 |
0 |
| T5 |
14137 |
254 |
0 |
0 |
| T6 |
16546 |
187 |
0 |
0 |
| T7 |
2508 |
1 |
0 |
0 |
| T8 |
1269 |
1 |
0 |
0 |
| T9 |
3527 |
244 |
0 |
0 |
| T10 |
9691 |
1 |
0 |
0 |
rePulse
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
16610245 |
253055 |
0 |
0 |
| T1 |
1250 |
17 |
0 |
0 |
| T2 |
2599 |
58 |
0 |
0 |
| T3 |
1122 |
19 |
0 |
0 |
| T4 |
1534 |
153 |
0 |
0 |
| T5 |
14137 |
134 |
0 |
0 |
| T6 |
16546 |
77 |
0 |
0 |
| T7 |
2508 |
1 |
0 |
0 |
| T8 |
1269 |
1 |
0 |
0 |
| T9 |
3527 |
182 |
0 |
0 |
| T10 |
9691 |
1 |
0 |
0 |
wePulse
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
16610245 |
233417 |
0 |
0 |
| T1 |
1250 |
10 |
0 |
0 |
| T2 |
2599 |
38 |
0 |
0 |
| T3 |
1122 |
11 |
0 |
0 |
| T4 |
1534 |
128 |
0 |
0 |
| T5 |
14137 |
120 |
0 |
0 |
| T6 |
16546 |
110 |
0 |
0 |
| T7 |
2508 |
0 |
0 |
0 |
| T8 |
1269 |
0 |
0 |
0 |
| T9 |
3527 |
62 |
0 |
0 |
| T10 |
9691 |
0 |
0 |
0 |
| T14 |
0 |
452 |
0 |
0 |
| T26 |
0 |
122 |
0 |
0 |
| T40 |
0 |
10 |
0 |
0 |