Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	48146433	101019	0	0
StatusRise_A	48146433	113195	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48146433	101019	0	0
T1	3750	6	0	0
T2	7797	27	0	0
T3	3366	6	0	0
T4	4602	42	0	0
T5	42411	41	0	0
T6	49638	41	0	0
T7	7524	3	0	0
T8	3807	0	0	0
T9	10581	9	0	0
T10	29073	6	0	0
T26	0	46	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48146433	113195	0	0
T1	3750	9	0	0
T2	7797	30	0	0
T3	3366	9	0	0
T4	4602	44	0	0
T5	42411	44	0	0
T6	49638	44	0	0
T7	7524	9	0	0
T8	3807	12	0	0
T9	10581	12	0	0
T10	29073	9	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	16048811	37536	0	0
StatusRise_A	16048811	41914	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16048811	37536	0	0
T1	1250	2	0	0
T2	2599	9	0	0
T3	1122	2	0	0
T4	1534	16	0	0
T5	14137	16	0	0
T6	16546	15	0	0
T7	2508	1	0	0
T8	1269	0	0	0
T9	3527	3	0	0
T10	9691	2	0	0
T26	0	18	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16048811	41914	0	0
T1	1250	3	0	0
T2	2599	10	0	0
T3	1122	3	0	0
T4	1534	17	0	0
T5	14137	17	0	0
T6	16546	16	0	0
T7	2508	3	0	0
T8	1269	4	0	0
T9	3527	4	0	0
T10	9691	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	16048811	37536	0	0
StatusRise_A	16048811	41916	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16048811	37536	0	0
T1	1250	2	0	0
T2	2599	9	0	0
T3	1122	2	0	0
T4	1534	16	0	0
T5	14137	16	0	0
T6	16546	15	0	0
T7	2508	1	0	0
T8	1269	0	0	0
T9	3527	3	0	0
T10	9691	2	0	0
T26	0	18	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16048811	41916	0	0
T1	1250	3	0	0
T2	2599	10	0	0
T3	1122	3	0	0
T4	1534	17	0	0
T5	14137	17	0	0
T6	16546	16	0	0
T7	2508	3	0	0
T8	1269	4	0	0
T9	3527	4	0	0
T10	9691	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	16048811	25947	0	0
StatusRise_A	16048811	29365	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16048811	25947	0	0
T1	1250	2	0	0
T2	2599	9	0	0
T3	1122	2	0	0
T4	1534	10	0	0
T5	14137	9	0	0
T6	16546	11	0	0
T7	2508	1	0	0
T8	1269	0	0	0
T9	3527	3	0	0
T10	9691	2	0	0
T26	0	10	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16048811	29365	0	0
T1	1250	3	0	0
T2	2599	10	0	0
T3	1122	3	0	0
T4	1534	10	0	0
T5	14137	10	0	0
T6	16546	12	0	0
T7	2508	3	0	0
T8	1269	4	0	0
T9	3527	4	0	0
T10	9691	3	0	0