Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

41                      
42         1/1            always_comb reset_or_disable = !rst_ni || disable_sva;
           Tests:       T1 T2 T3 
43         1/1            always_comb esc_reset_or_disable = !rst_esc_ni || disable_sva;
           Tests:       T1 T2 T3 
44         1/1            always_comb slow_reset_or_disable = !rst_slow_ni || disable_sva;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	16049334	9631	0	0
EscTimeoutStoppedByClReset_A	16048811	2207181	0	0
EscTimeoutTriggersReset_A	3729947	407	0	0
RomAllowActiveState_A	16048811	41502	0	0
RomAllowCheckGoodState_A	16048811	41549	0	0
RomBlockActiveState_A	16048811	26896	0	0
RomBlockCheckGoodState_A	16048811	332106	0	0
RomIntgChkDisFalse_A	16048811	15589448	0	0
RomIntgChkDisTrue_A	16048811	83276	0	0
RstreqChkEsctimeout_A	16048811	3030	0	0
RstreqChkFsmterm_A	16048811	160	0	0
RstreqChkGlbesc_A	16048811	3030	0	0
RstreqChkMainpd_A	16048811	660524	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16049334	9631	0	0
T10	9692	80	0	0
T11	0	42	0	0
T12	2019	0	0	0
T13	5419	0	0	0
T14	57741	0	0	0
T17	1491	0	0	0
T20	9269	0	0	0
T26	10005	0	0	0
T28	6661	0	0	0
T31	52717	0	0	0
T40	1186	0	0	0
T141	0	296	0	0
T142	0	75	0	0
T143	0	11	0	0
T144	0	58	0	0
T145	0	20	0	0
T146	0	243	0	0
T147	0	130	0	0
T148	0	153	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16048811	2207181	0	0
T1	1250	13	0	0
T2	2599	254	0	0
T3	1122	10	0	0
T4	1534	10	0	0
T5	14137	3356	0	0
T6	16546	3126	0	0
T7	2508	24	0	0
T8	1269	14	0	0
T9	3527	32	0	0
T10	9691	27	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3729947	407	0	0
T7	213	2	0	0
T8	433	0	0	0
T9	1005	0	0	0
T10	456	5	0	0
T11	0	3	0	0
T12	367	0	0	0
T13	422	0	0	0
T14	5915	0	0	0
T17	496	0	0	0
T26	2135	0	0	0
T40	384	0	0	0
T141	0	5	0	0
T142	0	6	0	0
T143	0	2	0	0
T144	0	4	0	0
T145	0	4	0	0
T146	0	5	0	0
T149	0	5	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16048811	41502	0	0
T1	1250	3	0	0
T2	2599	10	0	0
T3	1122	3	0	0
T4	1534	17	0	0
T5	14137	17	0	0
T6	16546	16	0	0
T7	2508	3	0	0
T8	1269	4	0	0
T9	3527	4	0	0
T10	9691	3	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16048811	41549	0	0
T1	1250	3	0	0
T2	2599	10	0	0
T3	1122	3	0	0
T4	1534	17	0	0
T5	14137	17	0	0
T6	16546	16	0	0
T7	2508	3	0	0
T8	1269	4	0	0
T9	3527	4	0	0
T10	9691	3	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16048811	26896	0	0
T13	5419	802	0	0
T15	3562	0	0	0
T16	25581	0	0	0
T20	9268	0	0	0
T27	0	202	0	0
T28	6660	0	0	0
T31	52716	0	0	0
T32	4375	0	0	0
T33	5514	0	0	0
T34	14730	0	0	0
T35	8902	0	0	0
T38	0	13	0	0
T77	0	35	0	0
T80	0	14	0	0
T150	0	1449	0	0
T151	0	18	0	0
T152	0	1099	0	0
T153	0	1194	0	0
T154	0	934	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16048811	332106	0	0
T3	1122	23	0	0
T4	1534	0	0	0
T5	14137	0	0	0
T6	16546	0	0	0
T7	2508	0	0	0
T8	1269	0	0	0
T9	3527	0	0	0
T10	9691	0	0	0
T13	0	662	0	0
T14	0	4103	0	0
T17	1490	0	0	0
T26	10004	0	0	0
T27	0	61	0	0
T31	0	3978	0	0
T32	0	69	0	0
T38	0	1214	0	0
T80	0	1296	0	0
T150	0	779	0	0
T155	0	412	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16048811	15589448	0	0
T1	1250	1187	0	0
T2	2599	2505	0	0
T3	1122	1023	0	0
T4	1534	1470	0	0
T5	14137	14037	0	0
T6	16546	16446	0	0
T7	2508	2372	0	0
T8	1269	961	0	0
T9	3527	3431	0	0
T10	9691	9630	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16048811	83276	0	0
T13	5419	244	0	0
T14	57740	1201	0	0
T15	3562	0	0	0
T20	9268	0	0	0
T27	0	307	0	0
T28	6660	0	0	0
T31	52716	0	0	0
T32	4375	0	0	0
T33	5514	0	0	0
T34	14730	0	0	0
T35	8902	0	0	0
T77	0	233	0	0
T80	0	304	0	0
T150	0	306	0	0
T152	0	2390	0	0
T153	0	1507	0	0
T156	0	2352	0	0
T157	0	600	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16048811	3030	0	0
T2	2599	5	0	0
T3	1122	0	0	0
T4	1534	0	0	0
T5	14137	0	0	0
T6	16546	0	0	0
T7	2508	1	0	0
T8	1269	3	0	0
T9	3527	0	0	0
T10	9691	2	0	0
T12	0	4	0	0
T13	0	1	0	0
T16	0	6	0	0
T20	0	10	0	0
T26	10004	0	0	0
T28	0	4	0	0
T33	0	9	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16048811	160	0	0
T11	2420	0	0	0
T15	3562	0	0	0
T16	25581	0	0	0
T20	9268	20	0	0
T21	0	40	0	0
T22	0	40	0	0
T29	0	40	0	0
T30	0	20	0	0
T31	52716	0	0	0
T32	4375	0	0	0
T33	5514	0	0	0
T34	14730	0	0	0
T35	8902	0	0	0
T36	2062	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16048811	3030	0	0
T2	2599	5	0	0
T3	1122	0	0	0
T4	1534	0	0	0
T5	14137	0	0	0
T6	16546	0	0	0
T7	2508	1	0	0
T8	1269	3	0	0
T9	3527	0	0	0
T10	9691	2	0	0
T12	0	4	0	0
T13	0	1	0	0
T16	0	6	0	0
T20	0	10	0	0
T26	10004	0	0	0
T28	0	4	0	0
T33	0	9	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16048811	660524	0	0
T2	2599	178	0	0
T3	1122	0	0	0
T4	1534	0	0	0
T5	14137	0	0	0
T6	16546	0	0	0
T7	2508	0	0	0
T8	1269	0	0	0
T9	3527	0	0	0
T10	9691	0	0	0
T13	0	1413	0	0
T14	0	4801	0	0
T16	0	418	0	0
T17	0	16	0	0
T26	10004	0	0	0
T28	0	92	0	0
T31	0	4596	0	0
T32	0	230	0	0
T33	0	631	0	0
T37	0	672	0	0