| T802 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1557757517 |
|
|
Oct 09 09:06:46 PM UTC 24 |
Oct 09 09:06:53 PM UTC 24 |
822619344 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_glitch.58370013 |
|
|
Oct 09 09:06:48 PM UTC 24 |
Oct 09 09:07:01 PM UTC 24 |
122839160 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_lowpower_invalid.1396754069 |
|
|
Oct 09 09:06:48 PM UTC 24 |
Oct 09 09:07:01 PM UTC 24 |
39378218 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_glitch.1816645615 |
|
|
Oct 09 09:06:46 PM UTC 24 |
Oct 09 09:07:01 PM UTC 24 |
65822816 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_lowpower_invalid.738494297 |
|
|
Oct 09 09:06:46 PM UTC 24 |
Oct 09 09:07:02 PM UTC 24 |
77516180 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_disable_rom_integrity_check.1750431189 |
|
|
Oct 09 09:06:46 PM UTC 24 |
Oct 09 09:07:02 PM UTC 24 |
60090395 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_wakeup_reset.3659945970 |
|
|
Oct 09 09:06:48 PM UTC 24 |
Oct 09 09:07:33 PM UTC 24 |
389489218 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_smoke.168806172 |
|
|
Oct 09 09:06:52 PM UTC 24 |
Oct 09 09:07:02 PM UTC 24 |
30787032 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_disable_rom_integrity_check.4288609758 |
|
|
Oct 09 09:06:48 PM UTC 24 |
Oct 09 09:07:02 PM UTC 24 |
61832253 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_escalation_timeout.3401577313 |
|
|
Oct 09 09:06:46 PM UTC 24 |
Oct 09 09:07:02 PM UTC 24 |
397192180 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_reset_invalid.2229452799 |
|
|
Oct 09 09:06:48 PM UTC 24 |
Oct 09 09:07:02 PM UTC 24 |
116858326 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_wakeup_reset.501341395 |
|
|
Oct 09 09:06:53 PM UTC 24 |
Oct 09 09:07:02 PM UTC 24 |
42265119 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_reset.2960058364 |
|
|
Oct 09 09:06:53 PM UTC 24 |
Oct 09 09:07:02 PM UTC 24 |
96147474 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_lowpower_wakeup_race.2714579286 |
|
|
Oct 09 09:06:53 PM UTC 24 |
Oct 09 09:07:02 PM UTC 24 |
154124253 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_reset.4253281339 |
|
|
Oct 09 09:06:50 PM UTC 24 |
Oct 09 09:07:02 PM UTC 24 |
45249710 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_esc_clk_rst_malfunc.718340811 |
|
|
Oct 09 09:06:53 PM UTC 24 |
Oct 09 09:07:02 PM UTC 24 |
29612158 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_aborted_low_power.1639510945 |
|
|
Oct 09 09:06:46 PM UTC 24 |
Oct 09 09:07:02 PM UTC 24 |
24166446 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_aborted_low_power.1998092415 |
|
|
Oct 09 09:06:53 PM UTC 24 |
Oct 09 09:07:02 PM UTC 24 |
48060676 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_smoke.113496804 |
|
|
Oct 09 09:06:50 PM UTC 24 |
Oct 09 09:07:02 PM UTC 24 |
27551660 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_sec_cm_rstmgr_intersig_mubi.1377222711 |
|
|
Oct 09 09:06:53 PM UTC 24 |
Oct 09 09:07:02 PM UTC 24 |
101022531 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_lowpower_wakeup_race.30224894 |
|
|
Oct 09 09:06:50 PM UTC 24 |
Oct 09 09:07:02 PM UTC 24 |
280839475 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_wakeup.1242589925 |
|
|
Oct 09 09:06:50 PM UTC 24 |
Oct 09 09:07:02 PM UTC 24 |
216841622 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_wakeup.2396597110 |
|
|
Oct 09 09:06:53 PM UTC 24 |
Oct 09 09:07:02 PM UTC 24 |
268381045 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_sec_cm_ctrl_config_regwen.2842101374 |
|
|
Oct 09 09:06:53 PM UTC 24 |
Oct 09 09:07:02 PM UTC 24 |
366164655 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_wakeup_reset.3199461516 |
|
|
Oct 09 09:06:50 PM UTC 24 |
Oct 09 09:07:03 PM UTC 24 |
212590644 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2019778035 |
|
|
Oct 09 09:06:48 PM UTC 24 |
Oct 09 09:07:03 PM UTC 24 |
783853564 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2343247087 |
|
|
Oct 09 09:06:50 PM UTC 24 |
Oct 09 09:07:03 PM UTC 24 |
1108504382 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3349247973 |
|
|
Oct 09 09:06:53 PM UTC 24 |
Oct 09 09:07:04 PM UTC 24 |
1216575441 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3137464457 |
|
|
Oct 09 09:06:53 PM UTC 24 |
Oct 09 09:07:04 PM UTC 24 |
876322947 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_reset_invalid.3527882018 |
|
|
Oct 09 09:06:50 PM UTC 24 |
Oct 09 09:07:05 PM UTC 24 |
239639536 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_stress_all.1974718369 |
|
|
Oct 09 09:06:50 PM UTC 24 |
Oct 09 09:07:06 PM UTC 24 |
1248074163 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_stress_all_with_rand_reset.40124662 |
|
|
Oct 09 09:06:46 PM UTC 24 |
Oct 09 09:07:09 PM UTC 24 |
2346565201 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_stress_all_with_rand_reset.3629897061 |
|
|
Oct 09 09:06:50 PM UTC 24 |
Oct 09 09:07:11 PM UTC 24 |
4980554108 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_lowpower_invalid.2028623953 |
|
|
Oct 09 09:07:02 PM UTC 24 |
Oct 09 09:07:11 PM UTC 24 |
161745898 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_aborted_low_power.413849624 |
|
|
Oct 09 09:07:06 PM UTC 24 |
Oct 09 09:07:21 PM UTC 24 |
53022548 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_smoke.3031192520 |
|
|
Oct 09 09:07:02 PM UTC 24 |
Oct 09 09:07:21 PM UTC 24 |
36971017 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_wakeup_reset.3641068236 |
|
|
Oct 09 09:07:06 PM UTC 24 |
Oct 09 09:07:21 PM UTC 24 |
51827596 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_reset.1765448296 |
|
|
Oct 09 09:07:02 PM UTC 24 |
Oct 09 09:07:22 PM UTC 24 |
90813316 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_wakeup.1465731145 |
|
|
Oct 09 09:07:03 PM UTC 24 |
Oct 09 09:07:22 PM UTC 24 |
184742897 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_reset_invalid.1698347828 |
|
|
Oct 09 09:07:02 PM UTC 24 |
Oct 09 09:07:22 PM UTC 24 |
468573848 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_lowpower_wakeup_race.1966972904 |
|
|
Oct 09 09:07:02 PM UTC 24 |
Oct 09 09:07:22 PM UTC 24 |
88030055 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_wakeup_reset.3037840793 |
|
|
Oct 09 09:07:03 PM UTC 24 |
Oct 09 09:07:22 PM UTC 24 |
135579062 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_rstmgr_intersig_mubi.3958606523 |
|
|
Oct 09 09:07:13 PM UTC 24 |
Oct 09 09:07:22 PM UTC 24 |
180878170 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_aborted_low_power.3318753901 |
|
|
Oct 09 09:07:03 PM UTC 24 |
Oct 09 09:07:22 PM UTC 24 |
21950144 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_stress_all.43633780 |
|
|
Oct 09 09:07:02 PM UTC 24 |
Oct 09 09:07:23 PM UTC 24 |
1234441515 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.440391068 |
|
|
Oct 09 09:07:03 PM UTC 24 |
Oct 09 09:07:23 PM UTC 24 |
896701427 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.693904640 |
|
|
Oct 09 09:07:10 PM UTC 24 |
Oct 09 09:07:23 PM UTC 24 |
799360239 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.844703364 |
|
|
Oct 09 09:07:03 PM UTC 24 |
Oct 09 09:07:24 PM UTC 24 |
958441627 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_reset.4037063315 |
|
|
Oct 09 09:06:48 PM UTC 24 |
Oct 09 09:07:26 PM UTC 24 |
67710848 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_lowpower_wakeup_race.4114711765 |
|
|
Oct 09 09:06:48 PM UTC 24 |
Oct 09 09:07:26 PM UTC 24 |
210136029 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_reset.3271119166 |
|
|
Oct 09 09:07:04 PM UTC 24 |
Oct 09 09:07:26 PM UTC 24 |
80022589 ps |
| T52 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_stress_all_with_rand_reset.2269367209 |
|
|
Oct 09 09:07:02 PM UTC 24 |
Oct 09 09:07:30 PM UTC 24 |
2611900465 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_glitch.3182891348 |
|
|
Oct 09 09:07:22 PM UTC 24 |
Oct 09 09:07:31 PM UTC 24 |
189246907 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_disable_rom_integrity_check.214625370 |
|
|
Oct 09 09:07:04 PM UTC 24 |
Oct 09 09:07:33 PM UTC 24 |
68794887 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_global_esc.3025076321 |
|
|
Oct 09 09:07:22 PM UTC 24 |
Oct 09 09:07:31 PM UTC 24 |
50302102 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_ctrl_config_regwen.881918381 |
|
|
Oct 09 09:07:22 PM UTC 24 |
Oct 09 09:07:31 PM UTC 24 |
163836193 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_disable_rom_integrity_check.12566695 |
|
|
Oct 09 09:07:22 PM UTC 24 |
Oct 09 09:07:31 PM UTC 24 |
62044707 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_escalation_timeout.2811473860 |
|
|
Oct 09 09:07:22 PM UTC 24 |
Oct 09 09:07:31 PM UTC 24 |
500245160 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_ctrl_config_regwen.1465113451 |
|
|
Oct 09 09:07:27 PM UTC 24 |
Oct 09 09:07:32 PM UTC 24 |
84660608 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_esc_clk_rst_malfunc.4144813425 |
|
|
Oct 09 09:07:27 PM UTC 24 |
Oct 09 09:07:32 PM UTC 24 |
41300655 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_global_esc.1288164158 |
|
|
Oct 09 09:07:27 PM UTC 24 |
Oct 09 09:07:32 PM UTC 24 |
73086423 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_esc_clk_rst_malfunc.3565674582 |
|
|
Oct 09 09:07:14 PM UTC 24 |
Oct 09 09:07:33 PM UTC 24 |
99873376 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_lowpower_invalid.2096840192 |
|
|
Oct 09 09:07:04 PM UTC 24 |
Oct 09 09:07:33 PM UTC 24 |
45417573 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_wakeup.2939838930 |
|
|
Oct 09 09:06:48 PM UTC 24 |
Oct 09 09:07:33 PM UTC 24 |
209211134 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_glitch.2971645569 |
|
|
Oct 09 09:06:54 PM UTC 24 |
Oct 09 09:07:33 PM UTC 24 |
100917892 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_aborted_low_power.2693159123 |
|
|
Oct 09 09:06:48 PM UTC 24 |
Oct 09 09:07:33 PM UTC 24 |
100053153 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_esc_clk_rst_malfunc.3791885704 |
|
|
Oct 09 09:07:04 PM UTC 24 |
Oct 09 09:07:33 PM UTC 24 |
45262378 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_disable_rom_integrity_check.3255977581 |
|
|
Oct 09 09:06:54 PM UTC 24 |
Oct 09 09:07:33 PM UTC 24 |
50902540 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_sec_cm_rstmgr_intersig_mubi.1297951447 |
|
|
Oct 09 09:07:04 PM UTC 24 |
Oct 09 09:07:33 PM UTC 24 |
127671068 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_escalation_timeout.2148817636 |
|
|
Oct 09 09:07:31 PM UTC 24 |
Oct 09 09:07:33 PM UTC 24 |
199923012 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_escalation_timeout.3003763719 |
|
|
Oct 09 09:07:04 PM UTC 24 |
Oct 09 09:07:33 PM UTC 24 |
219710280 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_escalation_timeout.119631244 |
|
|
Oct 09 09:06:54 PM UTC 24 |
Oct 09 09:07:33 PM UTC 24 |
389771974 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_reset_invalid.3964261487 |
|
|
Oct 09 09:07:04 PM UTC 24 |
Oct 09 09:07:33 PM UTC 24 |
110724439 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.454349893 |
|
|
Oct 09 09:06:48 PM UTC 24 |
Oct 09 09:07:34 PM UTC 24 |
1648405996 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_glitch.474382252 |
|
|
Oct 09 09:07:34 PM UTC 24 |
Oct 09 09:07:36 PM UTC 24 |
92106278 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_ctrl_config_regwen.3450377241 |
|
|
Oct 09 09:07:34 PM UTC 24 |
Oct 09 09:07:36 PM UTC 24 |
399607485 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_reset_invalid.1522973717 |
|
|
Oct 09 09:07:34 PM UTC 24 |
Oct 09 09:07:36 PM UTC 24 |
188381432 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_escalation_timeout.3323974554 |
|
|
Oct 09 09:07:34 PM UTC 24 |
Oct 09 09:07:36 PM UTC 24 |
442206070 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_lowpower_invalid.1727950526 |
|
|
Oct 09 09:07:34 PM UTC 24 |
Oct 09 09:07:36 PM UTC 24 |
39275589 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_disable_rom_integrity_check.4082370168 |
|
|
Oct 09 09:07:34 PM UTC 24 |
Oct 09 09:07:36 PM UTC 24 |
61500306 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_lowpower_invalid.1350907547 |
|
|
Oct 09 09:07:23 PM UTC 24 |
Oct 09 09:07:36 PM UTC 24 |
43238042 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_reset_invalid.2821962522 |
|
|
Oct 09 09:07:23 PM UTC 24 |
Oct 09 09:07:36 PM UTC 24 |
102515954 ps |
| T63 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_stress_all_with_rand_reset.517583038 |
|
|
Oct 09 09:06:51 PM UTC 24 |
Oct 09 09:07:36 PM UTC 24 |
3370303784 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_stress_all_with_rand_reset.3815432892 |
|
|
Oct 09 09:07:34 PM UTC 24 |
Oct 09 09:07:37 PM UTC 24 |
2060346143 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_stress_all.2394617185 |
|
|
Oct 09 09:07:34 PM UTC 24 |
Oct 09 09:07:37 PM UTC 24 |
1012292057 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_wakeup.1131395278 |
|
|
Oct 09 09:07:24 PM UTC 24 |
Oct 09 09:07:41 PM UTC 24 |
107678081 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_wakeup_reset.1462923744 |
|
|
Oct 09 09:07:25 PM UTC 24 |
Oct 09 09:07:41 PM UTC 24 |
364026476 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_stress_all_with_rand_reset.1801479584 |
|
|
Oct 09 09:07:23 PM UTC 24 |
Oct 09 09:07:41 PM UTC 24 |
6920295271 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4193397155 |
|
|
Oct 09 09:07:34 PM UTC 24 |
Oct 09 09:07:48 PM UTC 24 |
980224469 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_wakeup.2815594363 |
|
|
Oct 09 09:07:05 PM UTC 24 |
Oct 09 09:07:50 PM UTC 24 |
44507835 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_aborted_low_power.2721818405 |
|
|
Oct 09 09:07:26 PM UTC 24 |
Oct 09 09:07:51 PM UTC 24 |
38893944 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_stress_all.1554653644 |
|
|
Oct 09 09:07:32 PM UTC 24 |
Oct 09 09:07:53 PM UTC 24 |
1279845501 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3781930834 |
|
|
Oct 09 09:07:26 PM UTC 24 |
Oct 09 09:07:53 PM UTC 24 |
806209915 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_rstmgr_intersig_mubi.2322672183 |
|
|
Oct 09 09:07:26 PM UTC 24 |
Oct 09 09:07:58 PM UTC 24 |
74477097 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_lowpower_wakeup_race.1940953396 |
|
|
Oct 09 09:07:32 PM UTC 24 |
Oct 09 09:08:01 PM UTC 24 |
63157851 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_reset.1692426869 |
|
|
Oct 09 09:07:32 PM UTC 24 |
Oct 09 09:08:02 PM UTC 24 |
126131672 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_wakeup_reset.2237559981 |
|
|
Oct 09 09:07:32 PM UTC 24 |
Oct 09 09:08:02 PM UTC 24 |
93712914 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_aborted_low_power.2181333960 |
|
|
Oct 09 09:07:32 PM UTC 24 |
Oct 09 09:08:02 PM UTC 24 |
46203372 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_wakeup.770119837 |
|
|
Oct 09 09:07:32 PM UTC 24 |
Oct 09 09:08:02 PM UTC 24 |
269438309 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_esc_clk_rst_malfunc.3748860468 |
|
|
Oct 09 09:07:34 PM UTC 24 |
Oct 09 09:08:03 PM UTC 24 |
30045899 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_global_esc.1083515070 |
|
|
Oct 09 09:07:34 PM UTC 24 |
Oct 09 09:08:03 PM UTC 24 |
44193748 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_lowpower_wakeup_race.3178512538 |
|
|
Oct 09 09:07:05 PM UTC 24 |
Oct 09 09:08:05 PM UTC 24 |
271735270 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3685244793 |
|
|
Oct 09 09:07:26 PM UTC 24 |
Oct 09 09:08:08 PM UTC 24 |
868397726 ps |
| T58 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.2539032393 |
|
|
Oct 09 09:07:38 PM UTC 24 |
Oct 09 09:07:41 PM UTC 24 |
153312205 ps |
| T59 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.1398638703 |
|
|
Oct 09 09:07:38 PM UTC 24 |
Oct 09 09:07:43 PM UTC 24 |
606263473 ps |
| T55 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.454783759 |
|
|
Oct 09 09:07:37 PM UTC 24 |
Oct 09 09:07:46 PM UTC 24 |
100039963 ps |
| T66 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.204310995 |
|
|
Oct 09 09:07:37 PM UTC 24 |
Oct 09 09:07:46 PM UTC 24 |
92771462 ps |
| T56 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_intr_test.601863060 |
|
|
Oct 09 09:07:41 PM UTC 24 |
Oct 09 09:07:46 PM UTC 24 |
28703655 ps |
| T57 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.69881500 |
|
|
Oct 09 09:07:41 PM UTC 24 |
Oct 09 09:07:46 PM UTC 24 |
50955124 ps |
| T49 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_tl_errors.2927923243 |
|
|
Oct 09 09:07:34 PM UTC 24 |
Oct 09 09:07:46 PM UTC 24 |
268128039 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.1250997320 |
|
|
Oct 09 09:07:35 PM UTC 24 |
Oct 09 09:07:47 PM UTC 24 |
74060418 ps |
| T107 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_rw.726979031 |
|
|
Oct 09 09:07:35 PM UTC 24 |
Oct 09 09:07:50 PM UTC 24 |
134295320 ps |
| T117 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.3222493364 |
|
|
Oct 09 09:07:48 PM UTC 24 |
Oct 09 09:07:51 PM UTC 24 |
495258066 ps |
| T60 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.1450214755 |
|
|
Oct 09 09:07:49 PM UTC 24 |
Oct 09 09:07:51 PM UTC 24 |
55053177 ps |
| T50 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_tl_errors.146776348 |
|
|
Oct 09 09:07:46 PM UTC 24 |
Oct 09 09:07:52 PM UTC 24 |
182447589 ps |
| T166 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_intr_test.4184030939 |
|
|
Oct 09 09:07:51 PM UTC 24 |
Oct 09 09:07:53 PM UTC 24 |
29344742 ps |
| T118 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_rw.1636632497 |
|
|
Oct 09 09:07:42 PM UTC 24 |
Oct 09 09:07:55 PM UTC 24 |
28856529 ps |
| T167 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_intr_test.596046042 |
|
|
Oct 09 09:07:37 PM UTC 24 |
Oct 09 09:07:58 PM UTC 24 |
20653263 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_rw.1730767593 |
|
|
Oct 09 09:07:47 PM UTC 24 |
Oct 09 09:07:58 PM UTC 24 |
38494666 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_csr_rw.242541147 |
|
|
Oct 09 09:08:08 PM UTC 24 |
Oct 09 09:08:11 PM UTC 24 |
18760330 ps |
| T168 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_intr_test.5569197 |
|
|
Oct 09 09:07:35 PM UTC 24 |
Oct 09 09:08:00 PM UTC 24 |
34377919 ps |
| T169 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_intr_test.2942432162 |
|
|
Oct 09 09:07:56 PM UTC 24 |
Oct 09 09:08:00 PM UTC 24 |
19722434 ps |
| T171 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.74380074 |
|
|
Oct 09 09:07:48 PM UTC 24 |
Oct 09 09:08:01 PM UTC 24 |
98725871 ps |
| T109 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_rw.1675494615 |
|
|
Oct 09 09:07:52 PM UTC 24 |
Oct 09 09:08:01 PM UTC 24 |
65205499 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.2273006433 |
|
|
Oct 09 09:07:52 PM UTC 24 |
Oct 09 09:08:01 PM UTC 24 |
24439470 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_csr_rw.3759562548 |
|
|
Oct 09 09:07:57 PM UTC 24 |
Oct 09 09:08:01 PM UTC 24 |
35333497 ps |
| T121 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.3309907521 |
|
|
Oct 09 09:07:37 PM UTC 24 |
Oct 09 09:08:02 PM UTC 24 |
62244562 ps |
| T70 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.4134434049 |
|
|
Oct 09 09:07:37 PM UTC 24 |
Oct 09 09:08:02 PM UTC 24 |
114397019 ps |
| T122 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.1341232243 |
|
|
Oct 09 09:07:57 PM UTC 24 |
Oct 09 09:08:02 PM UTC 24 |
135379130 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.3722841290 |
|
|
Oct 09 09:07:40 PM UTC 24 |
Oct 09 09:08:02 PM UTC 24 |
84470553 ps |
| T53 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.4154928856 |
|
|
Oct 09 09:07:37 PM UTC 24 |
Oct 09 09:08:02 PM UTC 24 |
101067427 ps |
| T54 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_tl_errors.918317629 |
|
|
Oct 09 09:07:37 PM UTC 24 |
Oct 09 09:08:02 PM UTC 24 |
63393276 ps |
| T71 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_tl_errors.3779695048 |
|
|
Oct 09 09:07:59 PM UTC 24 |
Oct 09 09:08:02 PM UTC 24 |
33781895 ps |
| T170 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_intr_test.1767104177 |
|
|
Oct 09 09:08:08 PM UTC 24 |
Oct 09 09:08:11 PM UTC 24 |
45688656 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.136731869 |
|
|
Oct 09 09:07:52 PM UTC 24 |
Oct 09 09:08:02 PM UTC 24 |
226478271 ps |
| T68 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.2637363625 |
|
|
Oct 09 09:07:59 PM UTC 24 |
Oct 09 09:08:02 PM UTC 24 |
53742861 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.507393503 |
|
|
Oct 09 09:07:53 PM UTC 24 |
Oct 09 09:08:03 PM UTC 24 |
43442881 ps |
| T123 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.2724738770 |
|
|
Oct 09 09:07:53 PM UTC 24 |
Oct 09 09:08:03 PM UTC 24 |
68411130 ps |
| T61 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.1705857616 |
|
|
Oct 09 09:07:59 PM UTC 24 |
Oct 09 09:08:03 PM UTC 24 |
198220919 ps |
| T62 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.1497576684 |
|
|
Oct 09 09:07:35 PM UTC 24 |
Oct 09 09:08:05 PM UTC 24 |
95354235 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.114286120 |
|
|
Oct 09 09:08:02 PM UTC 24 |
Oct 09 09:08:05 PM UTC 24 |
49186528 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_csr_rw.1740411535 |
|
|
Oct 09 09:08:10 PM UTC 24 |
Oct 09 09:08:11 PM UTC 24 |
21163500 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.2187925011 |
|
|
Oct 09 09:07:42 PM UTC 24 |
Oct 09 09:08:03 PM UTC 24 |
170239828 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_intr_test.2999526684 |
|
|
Oct 09 09:07:47 PM UTC 24 |
Oct 09 09:08:03 PM UTC 24 |
44792831 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.3997498405 |
|
|
Oct 09 09:07:47 PM UTC 24 |
Oct 09 09:08:03 PM UTC 24 |
40234104 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_intr_test.3002391876 |
|
|
Oct 09 09:08:01 PM UTC 24 |
Oct 09 09:08:03 PM UTC 24 |
23909516 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_csr_rw.3784231864 |
|
|
Oct 09 09:08:01 PM UTC 24 |
Oct 09 09:08:03 PM UTC 24 |
18542790 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.1086135108 |
|
|
Oct 09 09:07:47 PM UTC 24 |
Oct 09 09:08:03 PM UTC 24 |
120361459 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_intr_test.86100119 |
|
|
Oct 09 09:08:08 PM UTC 24 |
Oct 09 09:08:11 PM UTC 24 |
37020438 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.554016095 |
|
|
Oct 09 09:08:01 PM UTC 24 |
Oct 09 09:08:03 PM UTC 24 |
68769125 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.3185519589 |
|
|
Oct 09 09:08:01 PM UTC 24 |
Oct 09 09:08:03 PM UTC 24 |
75683466 ps |
| T74 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_tl_errors.154350286 |
|
|
Oct 09 09:07:51 PM UTC 24 |
Oct 09 09:08:03 PM UTC 24 |
29371875 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.1205527422 |
|
|
Oct 09 09:07:36 PM UTC 24 |
Oct 09 09:08:03 PM UTC 24 |
258084162 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_tl_errors.423009166 |
|
|
Oct 09 09:08:01 PM UTC 24 |
Oct 09 09:08:04 PM UTC 24 |
46568993 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.4287475554 |
|
|
Oct 09 09:07:43 PM UTC 24 |
Oct 09 09:08:04 PM UTC 24 |
54755694 ps |
| T69 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_tl_errors.3347309248 |
|
|
Oct 09 09:07:40 PM UTC 24 |
Oct 09 09:08:04 PM UTC 24 |
153686325 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.1480184329 |
|
|
Oct 09 09:07:45 PM UTC 24 |
Oct 09 09:08:04 PM UTC 24 |
38442466 ps |
| T72 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.4098774923 |
|
|
Oct 09 09:07:41 PM UTC 24 |
Oct 09 09:08:04 PM UTC 24 |
114233864 ps |
| T162 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.1491656116 |
|
|
Oct 09 09:07:51 PM UTC 24 |
Oct 09 09:08:04 PM UTC 24 |
186490462 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.2400516722 |
|
|
Oct 09 09:08:08 PM UTC 24 |
Oct 09 09:08:12 PM UTC 24 |
247190031 ps |
| T75 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.2490797764 |
|
|
Oct 09 09:07:54 PM UTC 24 |
Oct 09 09:08:04 PM UTC 24 |
62838081 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_tl_errors.338937753 |
|
|
Oct 09 09:07:54 PM UTC 24 |
Oct 09 09:08:04 PM UTC 24 |
388959274 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_intr_test.2045226727 |
|
|
Oct 09 09:08:02 PM UTC 24 |
Oct 09 09:08:04 PM UTC 24 |
47925846 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_csr_rw.2237006299 |
|
|
Oct 09 09:08:02 PM UTC 24 |
Oct 09 09:08:05 PM UTC 24 |
17946238 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.1543802488 |
|
|
Oct 09 09:08:02 PM UTC 24 |
Oct 09 09:08:05 PM UTC 24 |
30903821 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_csr_rw.3362619391 |
|
|
Oct 09 09:08:03 PM UTC 24 |
Oct 09 09:08:05 PM UTC 24 |
23231839 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.3748860942 |
|
|
Oct 09 09:08:02 PM UTC 24 |
Oct 09 09:08:05 PM UTC 24 |
114559239 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.1220483006 |
|
|
Oct 09 09:08:03 PM UTC 24 |
Oct 09 09:08:05 PM UTC 24 |
31753561 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_csr_rw.2170177347 |
|
|
Oct 09 09:08:03 PM UTC 24 |
Oct 09 09:08:05 PM UTC 24 |
35045673 ps |
| T163 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.1718837438 |
|
|
Oct 09 09:08:08 PM UTC 24 |
Oct 09 09:08:12 PM UTC 24 |
236714957 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_intr_test.3794662145 |
|
|
Oct 09 09:08:03 PM UTC 24 |
Oct 09 09:08:05 PM UTC 24 |
19720100 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_intr_test.2739562641 |
|
|
Oct 09 09:08:03 PM UTC 24 |
Oct 09 09:08:05 PM UTC 24 |
24228404 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_tl_errors.3943282149 |
|
|
Oct 09 09:08:02 PM UTC 24 |
Oct 09 09:08:05 PM UTC 24 |
83586095 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.2199634760 |
|
|
Oct 09 09:07:46 PM UTC 24 |
Oct 09 09:08:05 PM UTC 24 |
72145943 ps |
| T73 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.3249044174 |
|
|
Oct 09 09:07:56 PM UTC 24 |
Oct 09 09:08:05 PM UTC 24 |
138980679 ps |
| T164 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.1693187437 |
|
|
Oct 09 09:08:03 PM UTC 24 |
Oct 09 09:08:05 PM UTC 24 |
116482634 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.332952469 |
|
|
Oct 09 09:08:03 PM UTC 24 |
Oct 09 09:08:05 PM UTC 24 |
47531449 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.2227945420 |
|
|
Oct 09 09:08:03 PM UTC 24 |
Oct 09 09:08:05 PM UTC 24 |
62487565 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_tl_errors.1531577738 |
|
|
Oct 09 09:08:03 PM UTC 24 |
Oct 09 09:08:06 PM UTC 24 |
63306025 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.1564452626 |
|
|
Oct 09 09:08:03 PM UTC 24 |
Oct 09 09:08:06 PM UTC 24 |
167262099 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.4024863330 |
|
|
Oct 09 09:08:03 PM UTC 24 |
Oct 09 09:08:06 PM UTC 24 |
105216735 ps |
| T165 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.2683594783 |
|
|
Oct 09 09:07:46 PM UTC 24 |
Oct 09 09:08:07 PM UTC 24 |
212843344 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_csr_rw.1837919553 |
|
|
Oct 09 09:08:08 PM UTC 24 |
Oct 09 09:08:11 PM UTC 24 |
47585344 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_tl_errors.11232650 |
|
|
Oct 09 09:08:08 PM UTC 24 |
Oct 09 09:08:13 PM UTC 24 |
273546036 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.507309962 |
|
|
Oct 09 09:08:08 PM UTC 24 |
Oct 09 09:08:11 PM UTC 24 |
52636162 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.3197793873 |
|
|
Oct 09 09:08:08 PM UTC 24 |
Oct 09 09:08:11 PM UTC 24 |
21776148 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.628181209 |
|
|
Oct 09 09:08:08 PM UTC 24 |
Oct 09 09:08:11 PM UTC 24 |
85969435 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.48740914 |
|
|
Oct 09 09:08:08 PM UTC 24 |
Oct 09 09:08:11 PM UTC 24 |
104961638 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.2101904512 |
|
|
Oct 09 09:08:08 PM UTC 24 |
Oct 09 09:08:11 PM UTC 24 |
84715404 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.3784113469 |
|
|
Oct 09 09:08:08 PM UTC 24 |
Oct 09 09:08:12 PM UTC 24 |
358510962 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_tl_errors.1812843138 |
|
|
Oct 09 09:08:08 PM UTC 24 |
Oct 09 09:08:12 PM UTC 24 |
159131999 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_tl_errors.1332549180 |
|
|
Oct 09 09:08:08 PM UTC 24 |
Oct 09 09:08:12 PM UTC 24 |
437908247 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.2715450221 |
|
|
Oct 09 09:08:13 PM UTC 24 |
Oct 09 09:08:16 PM UTC 24 |
49266098 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/20.pwrmgr_intr_test.238501986 |
|
|
Oct 09 09:08:13 PM UTC 24 |
Oct 09 09:08:16 PM UTC 24 |
19945042 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.1076265010 |
|
|
Oct 09 09:08:13 PM UTC 24 |
Oct 09 09:08:17 PM UTC 24 |
54368164 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_intr_test.57638282 |
|
|
Oct 09 09:08:10 PM UTC 24 |
Oct 09 09:08:21 PM UTC 24 |
17808236 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/36.pwrmgr_intr_test.3919424995 |
|
|
Oct 09 09:08:18 PM UTC 24 |
Oct 09 09:08:25 PM UTC 24 |
24822662 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/34.pwrmgr_intr_test.3264726742 |
|
|
Oct 09 09:08:18 PM UTC 24 |
Oct 09 09:08:25 PM UTC 24 |
31134149 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/35.pwrmgr_intr_test.1754802783 |
|
|
Oct 09 09:08:18 PM UTC 24 |
Oct 09 09:08:25 PM UTC 24 |
23406106 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_intr_test.2795248532 |
|
|
Oct 09 09:08:08 PM UTC 24 |
Oct 09 09:08:26 PM UTC 24 |
27515953 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.2330662944 |
|
|
Oct 09 09:08:08 PM UTC 24 |
Oct 09 09:08:26 PM UTC 24 |
68350551 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/21.pwrmgr_intr_test.3805908845 |
|
|
Oct 09 09:08:13 PM UTC 24 |
Oct 09 09:08:26 PM UTC 24 |
21394357 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.729551279 |
|
|
Oct 09 09:08:08 PM UTC 24 |
Oct 09 09:08:26 PM UTC 24 |
107429523 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/24.pwrmgr_intr_test.2384711312 |
|
|
Oct 09 09:08:13 PM UTC 24 |
Oct 09 09:08:26 PM UTC 24 |
70766031 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/23.pwrmgr_intr_test.1034608533 |
|
|
Oct 09 09:08:13 PM UTC 24 |
Oct 09 09:08:26 PM UTC 24 |
18754485 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/22.pwrmgr_intr_test.3450367420 |
|
|
Oct 09 09:08:13 PM UTC 24 |
Oct 09 09:08:26 PM UTC 24 |
223451387 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/26.pwrmgr_intr_test.2091722497 |
|
|
Oct 09 09:08:13 PM UTC 24 |
Oct 09 09:08:26 PM UTC 24 |
21818283 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/25.pwrmgr_intr_test.2288527866 |
|
|
Oct 09 09:08:13 PM UTC 24 |
Oct 09 09:08:26 PM UTC 24 |
22813822 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/29.pwrmgr_intr_test.1658145029 |
|
|
Oct 09 09:08:14 PM UTC 24 |
Oct 09 09:08:27 PM UTC 24 |
16761567 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/28.pwrmgr_intr_test.2156255383 |
|
|
Oct 09 09:08:13 PM UTC 24 |
Oct 09 09:08:27 PM UTC 24 |
186154771 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/27.pwrmgr_intr_test.1430572691 |
|
|
Oct 09 09:08:13 PM UTC 24 |
Oct 09 09:08:27 PM UTC 24 |
26708942 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_csr_rw.3806065961 |
|
|
Oct 09 09:08:08 PM UTC 24 |
Oct 09 09:08:27 PM UTC 24 |
23153210 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.1869675090 |
|
|
Oct 09 09:08:05 PM UTC 24 |
Oct 09 09:08:27 PM UTC 24 |
70514607 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.2611845308 |
|
|
Oct 09 09:08:05 PM UTC 24 |
Oct 09 09:08:27 PM UTC 24 |
40763107 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_intr_test.4156796298 |
|
|
Oct 09 09:08:05 PM UTC 24 |
Oct 09 09:08:27 PM UTC 24 |
25542758 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_csr_rw.2284702691 |
|
|
Oct 09 09:08:05 PM UTC 24 |
Oct 09 09:08:27 PM UTC 24 |
62497131 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/37.pwrmgr_intr_test.955791109 |
|
|
Oct 09 09:08:22 PM UTC 24 |
Oct 09 09:08:28 PM UTC 24 |
51471830 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_intr_test.215686413 |
|
|
Oct 09 09:08:05 PM UTC 24 |
Oct 09 09:08:28 PM UTC 24 |
20174974 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.1872645788 |
|
|
Oct 09 09:08:08 PM UTC 24 |
Oct 09 09:08:28 PM UTC 24 |
108748603 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.877661704 |
|
|
Oct 09 09:08:08 PM UTC 24 |
Oct 09 09:08:28 PM UTC 24 |
51705445 ps |
| T116 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_csr_rw.3075270769 |
|
|
Oct 09 09:08:08 PM UTC 24 |
Oct 09 09:08:28 PM UTC 24 |
20232808 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_csr_rw.512358577 |
|
|
Oct 09 09:08:05 PM UTC 24 |
Oct 09 09:08:28 PM UTC 24 |
56120149 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.4206186106 |
|
|
Oct 09 09:08:05 PM UTC 24 |
Oct 09 09:08:28 PM UTC 24 |
68016772 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.128335639 |
|
|
Oct 09 09:08:05 PM UTC 24 |
Oct 09 09:08:28 PM UTC 24 |
222941510 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.2579187289 |
|
|
Oct 09 09:08:05 PM UTC 24 |
Oct 09 09:08:28 PM UTC 24 |
47185687 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.3178314607 |
|
|
Oct 09 09:08:05 PM UTC 24 |
Oct 09 09:08:28 PM UTC 24 |
154190982 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_tl_errors.1580724048 |
|
|
Oct 09 09:08:08 PM UTC 24 |
Oct 09 09:08:28 PM UTC 24 |
75021774 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_tl_errors.3548108496 |
|
|
Oct 09 09:08:05 PM UTC 24 |
Oct 09 09:08:28 PM UTC 24 |
333757370 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_tl_errors.561430000 |
|
|
Oct 09 09:08:05 PM UTC 24 |
Oct 09 09:08:29 PM UTC 24 |
147721020 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/30.pwrmgr_intr_test.3507708145 |
|
|
Oct 09 09:08:15 PM UTC 24 |
Oct 09 09:08:30 PM UTC 24 |
62834966 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/32.pwrmgr_intr_test.126996034 |
|
|
Oct 09 09:08:15 PM UTC 24 |
Oct 09 09:08:30 PM UTC 24 |
62453978 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/31.pwrmgr_intr_test.3994317937 |
|
|
Oct 09 09:08:15 PM UTC 24 |
Oct 09 09:08:30 PM UTC 24 |
27124281 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_intr_test.1862129392 |
|
|
Oct 09 09:08:05 PM UTC 24 |
Oct 09 09:08:30 PM UTC 24 |
22825172 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/33.pwrmgr_intr_test.1804781372 |
|
|
Oct 09 09:08:15 PM UTC 24 |
Oct 09 09:08:30 PM UTC 24 |
20239089 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_csr_rw.3433359578 |
|
|
Oct 09 09:08:05 PM UTC 24 |
Oct 09 09:08:30 PM UTC 24 |
55652838 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_csr_rw.971826249 |
|
|
Oct 09 09:08:05 PM UTC 24 |
Oct 09 09:08:30 PM UTC 24 |
27091917 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_intr_test.1672786268 |
|
|
Oct 09 09:08:05 PM UTC 24 |
Oct 09 09:08:31 PM UTC 24 |
117780765 ps |
| T76 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.1534105378 |
|
|
Oct 09 09:08:05 PM UTC 24 |
Oct 09 09:08:31 PM UTC 24 |
222383358 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.1992384806 |
|
|
Oct 09 09:08:05 PM UTC 24 |
Oct 09 09:08:31 PM UTC 24 |
166772746 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.2919963808 |
|
|
Oct 09 09:08:05 PM UTC 24 |
Oct 09 09:08:31 PM UTC 24 |
24474630 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.4179137526 |
|
|
Oct 09 09:08:05 PM UTC 24 |
Oct 09 09:08:31 PM UTC 24 |
80822650 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.866552940 |
|
|
Oct 09 09:08:05 PM UTC 24 |
Oct 09 09:08:31 PM UTC 24 |
110636634 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/39.pwrmgr_intr_test.2388659291 |
|
|
Oct 09 09:08:26 PM UTC 24 |
Oct 09 09:08:31 PM UTC 24 |
19214288 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_intr_test.1304323737 |
|
|
Oct 09 09:08:06 PM UTC 24 |
Oct 09 09:08:31 PM UTC 24 |
47028804 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/38.pwrmgr_intr_test.680560745 |
|
|
Oct 09 09:08:26 PM UTC 24 |
Oct 09 09:08:31 PM UTC 24 |
48199184 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/42.pwrmgr_intr_test.2090116720 |
|
|
Oct 09 09:08:26 PM UTC 24 |
Oct 09 09:08:31 PM UTC 24 |
32813731 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/40.pwrmgr_intr_test.3364798376 |
|
|
Oct 09 09:08:26 PM UTC 24 |
Oct 09 09:08:31 PM UTC 24 |
19048756 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/41.pwrmgr_intr_test.892030271 |
|
|
Oct 09 09:08:26 PM UTC 24 |
Oct 09 09:08:31 PM UTC 24 |
28060559 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.3302320125 |
|
|
Oct 09 09:08:05 PM UTC 24 |
Oct 09 09:08:32 PM UTC 24 |
44945991 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_tl_errors.1286951349 |
|
|
Oct 09 09:08:05 PM UTC 24 |
Oct 09 09:08:32 PM UTC 24 |
130068977 ps |