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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.96 98.21 96.58 99.62 96.00 96.32 100.00 99.02


Total test records in report: 1117
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html

T557 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_aborted_low_power.3262318915 Oct 12 12:43:23 AM UTC 24 Oct 12 12:43:25 AM UTC 24 50541499 ps
T558 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_lowpower_wakeup_race.1139109278 Oct 12 12:41:07 AM UTC 24 Oct 12 12:41:09 AM UTC 24 251732207 ps
T559 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_glitch.2987702367 Oct 12 12:41:15 AM UTC 24 Oct 12 12:41:17 AM UTC 24 47780231 ps
T560 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_reset.63688764 Oct 12 12:41:07 AM UTC 24 Oct 12 12:41:10 AM UTC 24 32426701 ps
T561 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_esc_clk_rst_malfunc.2550761944 Oct 12 12:41:08 AM UTC 24 Oct 12 12:41:10 AM UTC 24 34531449 ps
T562 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_aborted_low_power.687447843 Oct 12 12:41:08 AM UTC 24 Oct 12 12:41:10 AM UTC 24 23987750 ps
T563 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_glitch.1470810870 Oct 12 12:41:08 AM UTC 24 Oct 12 12:41:10 AM UTC 24 45773795 ps
T564 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_wakeup_reset.1472834234 Oct 12 12:41:08 AM UTC 24 Oct 12 12:41:10 AM UTC 24 135844071 ps
T565 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_global_esc.3854272335 Oct 12 12:41:08 AM UTC 24 Oct 12 12:41:10 AM UTC 24 36302008 ps
T566 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_sec_cm_rstmgr_intersig_mubi.2430516491 Oct 12 12:41:08 AM UTC 24 Oct 12 12:41:10 AM UTC 24 105267197 ps
T567 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_wakeup.6473790 Oct 12 12:41:07 AM UTC 24 Oct 12 12:41:10 AM UTC 24 223378499 ps
T568 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_disable_rom_integrity_check.2906855001 Oct 12 12:41:08 AM UTC 24 Oct 12 12:41:10 AM UTC 24 72543893 ps
T569 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_escalation_timeout.2565299906 Oct 12 12:41:08 AM UTC 24 Oct 12 12:41:10 AM UTC 24 109529899 ps
T570 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_smoke.427657123 Oct 12 12:41:08 AM UTC 24 Oct 12 12:41:10 AM UTC 24 28494640 ps
T571 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_reset_invalid.1487045843 Oct 12 12:41:08 AM UTC 24 Oct 12 12:41:10 AM UTC 24 112737757 ps
T572 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_lowpower_invalid.3704367140 Oct 12 12:41:08 AM UTC 24 Oct 12 12:41:10 AM UTC 24 90563170 ps
T573 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_sec_cm_ctrl_config_regwen.2827122136 Oct 12 12:41:08 AM UTC 24 Oct 12 12:41:11 AM UTC 24 318667148 ps
T574 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_reset.3602312169 Oct 12 12:41:08 AM UTC 24 Oct 12 12:41:11 AM UTC 24 63932667 ps
T575 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_stress_all.302353582 Oct 12 12:41:08 AM UTC 24 Oct 12 12:41:11 AM UTC 24 84775656 ps
T576 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4242454066 Oct 12 12:41:08 AM UTC 24 Oct 12 12:41:12 AM UTC 24 857813351 ps
T577 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3237035435 Oct 12 12:41:08 AM UTC 24 Oct 12 12:41:12 AM UTC 24 827880674 ps
T578 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_stress_all.2261408620 Oct 12 12:41:07 AM UTC 24 Oct 12 12:41:12 AM UTC 24 5875569006 ps
T579 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_stress_all_with_rand_reset.607813380 Oct 12 12:41:07 AM UTC 24 Oct 12 12:41:13 AM UTC 24 1140140329 ps
T580 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_lowpower_wakeup_race.872589491 Oct 12 12:41:15 AM UTC 24 Oct 12 12:41:17 AM UTC 24 28583998 ps
T581 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_aborted_low_power.3312167101 Oct 12 12:41:15 AM UTC 24 Oct 12 12:41:17 AM UTC 24 83936277 ps
T582 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_wakeup.3436497275 Oct 12 12:41:15 AM UTC 24 Oct 12 12:41:17 AM UTC 24 92751523 ps
T583 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_wakeup_reset.144135037 Oct 12 12:41:15 AM UTC 24 Oct 12 12:41:17 AM UTC 24 264233619 ps
T584 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_global_esc.4216715497 Oct 12 12:41:15 AM UTC 24 Oct 12 12:41:17 AM UTC 24 93589936 ps
T585 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_sec_cm_rstmgr_intersig_mubi.2471489833 Oct 12 12:41:15 AM UTC 24 Oct 12 12:41:17 AM UTC 24 88210887 ps
T586 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_sec_cm_ctrl_config_regwen.2713840024 Oct 12 12:41:15 AM UTC 24 Oct 12 12:41:17 AM UTC 24 192580371 ps
T587 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_glitch.3243990503 Oct 12 12:42:17 AM UTC 24 Oct 12 12:42:19 AM UTC 24 67228699 ps
T588 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_smoke.127129769 Oct 12 12:41:16 AM UTC 24 Oct 12 12:41:17 AM UTC 24 64167691 ps
T589 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_lowpower_invalid.4741523 Oct 12 12:41:16 AM UTC 24 Oct 12 12:41:18 AM UTC 24 43935542 ps
T590 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_disable_rom_integrity_check.899848039 Oct 12 12:41:15 AM UTC 24 Oct 12 12:41:18 AM UTC 24 48907251 ps
T591 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_reset.2146199562 Oct 12 12:41:16 AM UTC 24 Oct 12 12:41:18 AM UTC 24 72084411 ps
T592 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_reset_invalid.3799546899 Oct 12 12:41:16 AM UTC 24 Oct 12 12:41:18 AM UTC 24 159820436 ps
T593 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_escalation_timeout.1427754967 Oct 12 12:41:15 AM UTC 24 Oct 12 12:41:18 AM UTC 24 393846513 ps
T594 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_wakeup.3053001820 Oct 12 12:41:16 AM UTC 24 Oct 12 12:41:18 AM UTC 24 112040766 ps
T595 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_lowpower_wakeup_race.3764355560 Oct 12 12:41:16 AM UTC 24 Oct 12 12:41:18 AM UTC 24 105666338 ps
T596 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3879779758 Oct 12 12:41:15 AM UTC 24 Oct 12 12:41:18 AM UTC 24 967098751 ps
T597 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2312874146 Oct 12 12:41:15 AM UTC 24 Oct 12 12:41:19 AM UTC 24 861174815 ps
T598 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_stress_all.3844129769 Oct 12 12:41:16 AM UTC 24 Oct 12 12:41:19 AM UTC 24 1043561863 ps
T78 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_stress_all_with_rand_reset.3763288635 Oct 12 12:41:08 AM UTC 24 Oct 12 12:41:20 AM UTC 24 3407839263 ps
T599 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_stress_all_with_rand_reset.2943865301 Oct 12 12:41:16 AM UTC 24 Oct 12 12:41:22 AM UTC 24 8995816575 ps
T600 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_aborted_low_power.2394503891 Oct 12 12:41:25 AM UTC 24 Oct 12 12:41:27 AM UTC 24 28342827 ps
T601 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_wakeup_reset.3160893142 Oct 12 12:41:25 AM UTC 24 Oct 12 12:41:27 AM UTC 24 99328121 ps
T602 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_glitch.2412022149 Oct 12 12:41:25 AM UTC 24 Oct 12 12:41:27 AM UTC 24 55383936 ps
T603 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_esc_clk_rst_malfunc.3424788011 Oct 12 12:41:25 AM UTC 24 Oct 12 12:41:27 AM UTC 24 32193162 ps
T604 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_global_esc.867772764 Oct 12 12:41:25 AM UTC 24 Oct 12 12:41:27 AM UTC 24 43040556 ps
T605 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_disable_rom_integrity_check.2598960087 Oct 12 12:41:25 AM UTC 24 Oct 12 12:41:27 AM UTC 24 72585238 ps
T606 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_lowpower_invalid.2008082967 Oct 12 12:41:25 AM UTC 24 Oct 12 12:41:27 AM UTC 24 72646413 ps
T607 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_sec_cm_rstmgr_intersig_mubi.1226848254 Oct 12 12:41:25 AM UTC 24 Oct 12 12:41:27 AM UTC 24 192847547 ps
T608 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_lowpower_wakeup_race.2768087472 Oct 12 12:41:44 AM UTC 24 Oct 12 12:41:46 AM UTC 24 178937752 ps
T609 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_wakeup_reset.2421620374 Oct 12 12:41:26 AM UTC 24 Oct 12 12:41:27 AM UTC 24 48508375 ps
T610 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_smoke.4129187695 Oct 12 12:41:26 AM UTC 24 Oct 12 12:41:27 AM UTC 24 70930941 ps
T611 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_reset_invalid.1068107495 Oct 12 12:41:25 AM UTC 24 Oct 12 12:41:27 AM UTC 24 152699344 ps
T612 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_lowpower_invalid.1434198635 Oct 12 12:41:44 AM UTC 24 Oct 12 12:41:46 AM UTC 24 83602258 ps
T613 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_escalation_timeout.2419173831 Oct 12 12:41:25 AM UTC 24 Oct 12 12:41:27 AM UTC 24 448542636 ps
T614 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_sec_cm_ctrl_config_regwen.1753592825 Oct 12 12:41:25 AM UTC 24 Oct 12 12:41:28 AM UTC 24 281816939 ps
T615 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_reset.1284235943 Oct 12 12:41:26 AM UTC 24 Oct 12 12:41:28 AM UTC 24 91110328 ps
T616 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_aborted_low_power.4276891855 Oct 12 12:41:26 AM UTC 24 Oct 12 12:41:28 AM UTC 24 36728370 ps
T617 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_lowpower_wakeup_race.356986720 Oct 12 12:41:26 AM UTC 24 Oct 12 12:41:28 AM UTC 24 233466724 ps
T618 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_esc_clk_rst_malfunc.1911449066 Oct 12 12:41:26 AM UTC 24 Oct 12 12:41:28 AM UTC 24 29249875 ps
T619 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_sec_cm_rstmgr_intersig_mubi.448228772 Oct 12 12:41:26 AM UTC 24 Oct 12 12:41:28 AM UTC 24 101149554 ps
T620 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2393086734 Oct 12 12:41:25 AM UTC 24 Oct 12 12:41:28 AM UTC 24 1434230215 ps
T621 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_wakeup.1863916253 Oct 12 12:41:26 AM UTC 24 Oct 12 12:41:28 AM UTC 24 189385468 ps
T622 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_sec_cm_ctrl_config_regwen.2258131672 Oct 12 12:41:26 AM UTC 24 Oct 12 12:41:28 AM UTC 24 287479792 ps
T623 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3345387609 Oct 12 12:41:25 AM UTC 24 Oct 12 12:41:29 AM UTC 24 765248737 ps
T624 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_stress_all.3694739092 Oct 12 12:41:26 AM UTC 24 Oct 12 12:41:30 AM UTC 24 1286092595 ps
T625 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2492660987 Oct 12 12:41:26 AM UTC 24 Oct 12 12:41:30 AM UTC 24 823157760 ps
T626 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2626258944 Oct 12 12:41:26 AM UTC 24 Oct 12 12:41:30 AM UTC 24 834043486 ps
T627 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_stress_all_with_rand_reset.995343321 Oct 12 12:41:25 AM UTC 24 Oct 12 12:41:34 AM UTC 24 3247714030 ps
T628 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_global_esc.3839684666 Oct 12 12:41:34 AM UTC 24 Oct 12 12:41:36 AM UTC 24 190311980 ps
T629 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_wakeup.1457462091 Oct 12 12:42:17 AM UTC 24 Oct 12 12:42:19 AM UTC 24 252653431 ps
T630 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_disable_rom_integrity_check.3845583649 Oct 12 12:41:34 AM UTC 24 Oct 12 12:41:36 AM UTC 24 63757418 ps
T631 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_glitch.1708920777 Oct 12 12:41:34 AM UTC 24 Oct 12 12:41:36 AM UTC 24 48055970 ps
T632 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_escalation_timeout.2832702462 Oct 12 12:41:34 AM UTC 24 Oct 12 12:41:36 AM UTC 24 493531276 ps
T633 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_lowpower_invalid.1663617016 Oct 12 12:41:34 AM UTC 24 Oct 12 12:41:36 AM UTC 24 75489078 ps
T634 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_reset.3875082725 Oct 12 12:41:34 AM UTC 24 Oct 12 12:41:36 AM UTC 24 38962660 ps
T635 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_lowpower_wakeup_race.760500077 Oct 12 12:41:35 AM UTC 24 Oct 12 12:41:36 AM UTC 24 93298359 ps
T636 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_reset_invalid.1430905810 Oct 12 12:41:34 AM UTC 24 Oct 12 12:41:36 AM UTC 24 117189503 ps
T637 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_smoke.2863336767 Oct 12 12:41:34 AM UTC 24 Oct 12 12:41:36 AM UTC 24 31592541 ps
T638 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_wakeup.198750792 Oct 12 12:41:35 AM UTC 24 Oct 12 12:41:37 AM UTC 24 76498394 ps
T639 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_glitch.787493009 Oct 12 12:41:35 AM UTC 24 Oct 12 12:41:37 AM UTC 24 67663774 ps
T640 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_global_esc.3693555320 Oct 12 12:41:35 AM UTC 24 Oct 12 12:41:37 AM UTC 24 46800398 ps
T641 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_wakeup_reset.2501286762 Oct 12 12:41:35 AM UTC 24 Oct 12 12:41:37 AM UTC 24 259435072 ps
T642 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_aborted_low_power.721830616 Oct 12 12:41:35 AM UTC 24 Oct 12 12:41:37 AM UTC 24 36611252 ps
T643 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_sec_cm_rstmgr_intersig_mubi.2321863520 Oct 12 12:41:35 AM UTC 24 Oct 12 12:41:37 AM UTC 24 238069114 ps
T644 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_esc_clk_rst_malfunc.3163089154 Oct 12 12:41:35 AM UTC 24 Oct 12 12:41:37 AM UTC 24 33254345 ps
T645 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_stress_all.2863733913 Oct 12 12:41:34 AM UTC 24 Oct 12 12:41:37 AM UTC 24 437106141 ps
T646 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_sec_cm_ctrl_config_regwen.1033530411 Oct 12 12:41:35 AM UTC 24 Oct 12 12:41:37 AM UTC 24 125114273 ps
T178 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_disable_rom_integrity_check.1006369934 Oct 12 12:41:35 AM UTC 24 Oct 12 12:41:37 AM UTC 24 61649079 ps
T647 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_escalation_timeout.3056529166 Oct 12 12:41:35 AM UTC 24 Oct 12 12:41:37 AM UTC 24 116042981 ps
T648 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_reset_invalid.3102357488 Oct 12 12:41:35 AM UTC 24 Oct 12 12:41:37 AM UTC 24 107706633 ps
T649 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.800248256 Oct 12 12:41:35 AM UTC 24 Oct 12 12:41:38 AM UTC 24 1187466475 ps
T650 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3181075067 Oct 12 12:41:35 AM UTC 24 Oct 12 12:41:39 AM UTC 24 837542678 ps
T100 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_stress_all_with_rand_reset.1343209503 Oct 12 12:41:34 AM UTC 24 Oct 12 12:41:42 AM UTC 24 1540155622 ps
T651 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_smoke.3016273174 Oct 12 12:41:44 AM UTC 24 Oct 12 12:41:46 AM UTC 24 80661660 ps
T652 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_wakeup_reset.337937271 Oct 12 12:41:44 AM UTC 24 Oct 12 12:41:46 AM UTC 24 93738489 ps
T653 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_global_esc.2341371481 Oct 12 12:42:17 AM UTC 24 Oct 12 12:42:19 AM UTC 24 60293137 ps
T654 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2488666976 Oct 12 12:42:06 AM UTC 24 Oct 12 12:42:09 AM UTC 24 1173913931 ps
T655 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_reset.954706549 Oct 12 12:42:16 AM UTC 24 Oct 12 12:42:19 AM UTC 24 78047224 ps
T656 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_esc_clk_rst_malfunc.2283564767 Oct 12 12:41:45 AM UTC 24 Oct 12 12:41:46 AM UTC 24 29707757 ps
T657 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_global_esc.3919321701 Oct 12 12:41:45 AM UTC 24 Oct 12 12:41:46 AM UTC 24 46154813 ps
T658 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_reset.3519950574 Oct 12 12:41:44 AM UTC 24 Oct 12 12:41:46 AM UTC 24 73886873 ps
T659 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_glitch.2403884796 Oct 12 12:41:45 AM UTC 24 Oct 12 12:41:46 AM UTC 24 48160059 ps
T660 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_wakeup.2177910826 Oct 12 12:41:44 AM UTC 24 Oct 12 12:41:47 AM UTC 24 283183934 ps
T661 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_smoke.6428984 Oct 12 12:42:16 AM UTC 24 Oct 12 12:42:19 AM UTC 24 118947236 ps
T662 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_aborted_low_power.2999215076 Oct 12 12:41:44 AM UTC 24 Oct 12 12:41:47 AM UTC 24 83047067 ps
T663 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_sec_cm_rstmgr_intersig_mubi.4157913201 Oct 12 12:41:44 AM UTC 24 Oct 12 12:41:47 AM UTC 24 99651268 ps
T664 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_lowpower_invalid.2923954091 Oct 12 12:42:16 AM UTC 24 Oct 12 12:42:18 AM UTC 24 45859610 ps
T665 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_disable_rom_integrity_check.2950165258 Oct 12 12:41:45 AM UTC 24 Oct 12 12:41:47 AM UTC 24 73319042 ps
T666 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_lowpower_invalid.1370437928 Oct 12 12:41:45 AM UTC 24 Oct 12 12:41:47 AM UTC 24 43243890 ps
T667 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_sec_cm_ctrl_config_regwen.1666948941 Oct 12 12:41:45 AM UTC 24 Oct 12 12:41:47 AM UTC 24 122524915 ps
T668 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_wakeup.888604914 Oct 12 12:41:45 AM UTC 24 Oct 12 12:41:47 AM UTC 24 58030398 ps
T669 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_escalation_timeout.3867996665 Oct 12 12:41:45 AM UTC 24 Oct 12 12:41:47 AM UTC 24 1545382599 ps
T670 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_reset_invalid.3792108229 Oct 12 12:41:45 AM UTC 24 Oct 12 12:41:47 AM UTC 24 98970015 ps
T671 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_reset.1282094356 Oct 12 12:41:45 AM UTC 24 Oct 12 12:41:47 AM UTC 24 334278708 ps
T672 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_smoke.3827867440 Oct 12 12:41:45 AM UTC 24 Oct 12 12:41:47 AM UTC 24 30345872 ps
T673 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_lowpower_wakeup_race.559484710 Oct 12 12:41:45 AM UTC 24 Oct 12 12:41:47 AM UTC 24 195632916 ps
T674 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2917006110 Oct 12 12:41:44 AM UTC 24 Oct 12 12:41:47 AM UTC 24 995959890 ps
T675 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3925703665 Oct 12 12:41:44 AM UTC 24 Oct 12 12:41:48 AM UTC 24 1208846145 ps
T676 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_stress_all.4168188812 Oct 12 12:41:45 AM UTC 24 Oct 12 12:41:49 AM UTC 24 1951655368 ps
T677 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_stress_all.3108936769 Oct 12 12:41:44 AM UTC 24 Oct 12 12:41:51 AM UTC 24 1566008056 ps
T678 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_stress_all_with_rand_reset.570868340 Oct 12 12:41:44 AM UTC 24 Oct 12 12:41:52 AM UTC 24 2660602161 ps
T679 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_aborted_low_power.3779096016 Oct 12 12:41:54 AM UTC 24 Oct 12 12:41:56 AM UTC 24 119972143 ps
T680 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_esc_clk_rst_malfunc.2664950071 Oct 12 12:41:54 AM UTC 24 Oct 12 12:41:56 AM UTC 24 29705289 ps
T681 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_global_esc.1897495101 Oct 12 12:41:54 AM UTC 24 Oct 12 12:41:56 AM UTC 24 24751434 ps
T682 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_wakeup_reset.164582818 Oct 12 12:41:54 AM UTC 24 Oct 12 12:41:56 AM UTC 24 219539510 ps
T683 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_sec_cm_ctrl_config_regwen.452843959 Oct 12 12:41:54 AM UTC 24 Oct 12 12:41:56 AM UTC 24 1034205856 ps
T684 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_glitch.1280463586 Oct 12 12:41:54 AM UTC 24 Oct 12 12:41:56 AM UTC 24 64120931 ps
T685 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_smoke.1528989840 Oct 12 12:41:55 AM UTC 24 Oct 12 12:41:56 AM UTC 24 45758783 ps
T686 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_escalation_timeout.1141063838 Oct 12 12:41:54 AM UTC 24 Oct 12 12:41:57 AM UTC 24 111466658 ps
T687 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_sec_cm_rstmgr_intersig_mubi.2073538373 Oct 12 12:41:54 AM UTC 24 Oct 12 12:41:57 AM UTC 24 67333218 ps
T688 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_reset_invalid.2686870232 Oct 12 12:41:55 AM UTC 24 Oct 12 12:41:57 AM UTC 24 165507242 ps
T689 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_disable_rom_integrity_check.3199320934 Oct 12 12:41:54 AM UTC 24 Oct 12 12:41:57 AM UTC 24 73491818 ps
T690 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_lowpower_invalid.667742455 Oct 12 12:41:55 AM UTC 24 Oct 12 12:41:57 AM UTC 24 50769961 ps
T691 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_stress_all.1449579171 Oct 12 12:41:55 AM UTC 24 Oct 12 12:41:57 AM UTC 24 200974751 ps
T692 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_aborted_low_power.3911388591 Oct 12 12:41:55 AM UTC 24 Oct 12 12:41:57 AM UTC 24 35531746 ps
T693 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_reset.2361697526 Oct 12 12:41:55 AM UTC 24 Oct 12 12:41:57 AM UTC 24 80887941 ps
T694 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_lowpower_wakeup_race.3961748981 Oct 12 12:41:55 AM UTC 24 Oct 12 12:41:57 AM UTC 24 195070993 ps
T695 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_sec_cm_rstmgr_intersig_mubi.1016471120 Oct 12 12:41:55 AM UTC 24 Oct 12 12:41:57 AM UTC 24 176725436 ps
T696 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_wakeup.253004808 Oct 12 12:41:55 AM UTC 24 Oct 12 12:41:57 AM UTC 24 297394577 ps
T697 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1010082009 Oct 12 12:41:54 AM UTC 24 Oct 12 12:41:57 AM UTC 24 1685700398 ps
T698 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_wakeup_reset.2649844021 Oct 12 12:41:55 AM UTC 24 Oct 12 12:41:57 AM UTC 24 394298618 ps
T699 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3733869615 Oct 12 12:41:54 AM UTC 24 Oct 12 12:41:58 AM UTC 24 1225092696 ps
T700 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1803368509 Oct 12 12:41:55 AM UTC 24 Oct 12 12:41:58 AM UTC 24 1030553728 ps
T701 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.898569047 Oct 12 12:41:55 AM UTC 24 Oct 12 12:41:58 AM UTC 24 1242589430 ps
T79 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_stress_all_with_rand_reset.3322851756 Oct 12 12:41:55 AM UTC 24 Oct 12 12:42:02 AM UTC 24 4273807210 ps
T80 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_stress_all_with_rand_reset.3829716555 Oct 12 12:41:45 AM UTC 24 Oct 12 12:42:03 AM UTC 24 13388511591 ps
T702 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_esc_clk_rst_malfunc.2308675291 Oct 12 12:42:05 AM UTC 24 Oct 12 12:42:07 AM UTC 24 57240188 ps
T703 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_global_esc.1617265139 Oct 12 12:42:05 AM UTC 24 Oct 12 12:42:07 AM UTC 24 47788062 ps
T704 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_glitch.2684206870 Oct 12 12:42:05 AM UTC 24 Oct 12 12:42:07 AM UTC 24 48438675 ps
T705 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_disable_rom_integrity_check.784031143 Oct 12 12:42:05 AM UTC 24 Oct 12 12:42:07 AM UTC 24 61571434 ps
T706 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_sec_cm_ctrl_config_regwen.161094558 Oct 12 12:42:05 AM UTC 24 Oct 12 12:42:07 AM UTC 24 439551923 ps
T707 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_escalation_timeout.87613949 Oct 12 12:42:05 AM UTC 24 Oct 12 12:42:07 AM UTC 24 113419633 ps
T708 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_lowpower_invalid.1770996016 Oct 12 12:42:05 AM UTC 24 Oct 12 12:42:07 AM UTC 24 240560573 ps
T709 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_smoke.1725834235 Oct 12 12:42:05 AM UTC 24 Oct 12 12:42:07 AM UTC 24 40164859 ps
T710 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_stress_all_with_rand_reset.703594594 Oct 12 12:42:05 AM UTC 24 Oct 12 12:42:10 AM UTC 24 2028016619 ps
T711 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_reset.4092002532 Oct 12 12:42:05 AM UTC 24 Oct 12 12:42:07 AM UTC 24 114257957 ps
T712 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_reset_invalid.747660009 Oct 12 12:42:05 AM UTC 24 Oct 12 12:42:07 AM UTC 24 105949762 ps
T713 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_esc_clk_rst_malfunc.3516873452 Oct 12 12:42:06 AM UTC 24 Oct 12 12:42:07 AM UTC 24 30244794 ps
T714 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_wakeup_reset.1264650726 Oct 12 12:42:05 AM UTC 24 Oct 12 12:42:07 AM UTC 24 181049144 ps
T715 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_sec_cm_rstmgr_intersig_mubi.1450483474 Oct 12 12:42:06 AM UTC 24 Oct 12 12:42:07 AM UTC 24 89539018 ps
T716 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_global_esc.1945021124 Oct 12 12:42:06 AM UTC 24 Oct 12 12:42:08 AM UTC 24 96259309 ps
T717 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_aborted_low_power.2439650100 Oct 12 12:42:05 AM UTC 24 Oct 12 12:42:08 AM UTC 24 47813572 ps
T718 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_wakeup.4021413128 Oct 12 12:42:05 AM UTC 24 Oct 12 12:42:08 AM UTC 24 161834623 ps
T719 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_lowpower_wakeup_race.578911538 Oct 12 12:42:05 AM UTC 24 Oct 12 12:42:08 AM UTC 24 318212492 ps
T720 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_glitch.3657705927 Oct 12 12:42:06 AM UTC 24 Oct 12 12:42:08 AM UTC 24 89729789 ps
T721 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_escalation_timeout.1318049114 Oct 12 12:42:06 AM UTC 24 Oct 12 12:42:08 AM UTC 24 500393612 ps
T722 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_reset_invalid.540955357 Oct 12 12:42:06 AM UTC 24 Oct 12 12:42:08 AM UTC 24 150882111 ps
T723 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_disable_rom_integrity_check.1315024626 Oct 12 12:42:06 AM UTC 24 Oct 12 12:42:08 AM UTC 24 51267930 ps
T724 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_sec_cm_ctrl_config_regwen.1005522044 Oct 12 12:42:06 AM UTC 24 Oct 12 12:42:08 AM UTC 24 274832148 ps
T725 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_stress_all.1669590703 Oct 12 12:42:05 AM UTC 24 Oct 12 12:42:08 AM UTC 24 548738819 ps
T726 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2935960210 Oct 12 12:42:06 AM UTC 24 Oct 12 12:42:09 AM UTC 24 1144228448 ps
T727 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_sec_cm_ctrl_config_regwen.4040548273 Oct 12 12:42:17 AM UTC 24 Oct 12 12:42:19 AM UTC 24 226576358 ps
T728 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_wakeup_reset.2249153028 Oct 12 12:42:17 AM UTC 24 Oct 12 12:42:19 AM UTC 24 245971307 ps
T729 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_lowpower_wakeup_race.4244075202 Oct 12 12:42:17 AM UTC 24 Oct 12 12:42:19 AM UTC 24 141019583 ps
T730 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_escalation_timeout.363482933 Oct 12 12:42:17 AM UTC 24 Oct 12 12:42:19 AM UTC 24 791782476 ps
T731 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_reset_invalid.1180376142 Oct 12 12:42:17 AM UTC 24 Oct 12 12:42:19 AM UTC 24 164144806 ps
T732 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_sec_cm_rstmgr_intersig_mubi.86667502 Oct 12 12:42:17 AM UTC 24 Oct 12 12:42:19 AM UTC 24 75465006 ps
T176 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_disable_rom_integrity_check.2557996002 Oct 12 12:42:17 AM UTC 24 Oct 12 12:42:19 AM UTC 24 52328003 ps
T733 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_smoke.3790383991 Oct 12 12:42:17 AM UTC 24 Oct 12 12:42:19 AM UTC 24 45215910 ps
T734 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_lowpower_invalid.1975567337 Oct 12 12:42:17 AM UTC 24 Oct 12 12:42:20 AM UTC 24 52023191 ps
T735 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_lowpower_wakeup_race.2325711169 Oct 12 12:42:17 AM UTC 24 Oct 12 12:42:20 AM UTC 24 180648202 ps
T736 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_reset.2043755311 Oct 12 12:42:17 AM UTC 24 Oct 12 12:42:20 AM UTC 24 40636253 ps
T737 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_wakeup.1922071850 Oct 12 12:42:17 AM UTC 24 Oct 12 12:42:20 AM UTC 24 354364846 ps
T738 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_aborted_low_power.3263677642 Oct 12 12:42:17 AM UTC 24 Oct 12 12:42:20 AM UTC 24 281990576 ps
T739 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2314251451 Oct 12 12:42:17 AM UTC 24 Oct 12 12:42:20 AM UTC 24 1694881366 ps
T740 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_wakeup_reset.2665747050 Oct 12 12:42:17 AM UTC 24 Oct 12 12:42:20 AM UTC 24 329042553 ps
T741 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2945905014 Oct 12 12:42:17 AM UTC 24 Oct 12 12:42:21 AM UTC 24 1293287895 ps
T742 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_stress_all.3011549655 Oct 12 12:42:17 AM UTC 24 Oct 12 12:42:21 AM UTC 24 1002778947 ps
T743 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_stress_all.3026624231 Oct 12 12:42:16 AM UTC 24 Oct 12 12:42:22 AM UTC 24 1756971174 ps
T147 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_stress_all_with_rand_reset.2301122858 Oct 12 12:42:16 AM UTC 24 Oct 12 12:42:24 AM UTC 24 6653000395 ps
T744 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_sec_cm_rstmgr_intersig_mubi.31797901 Oct 12 12:42:28 AM UTC 24 Oct 12 12:42:31 AM UTC 24 85192635 ps
T745 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_esc_clk_rst_malfunc.89786396 Oct 12 12:42:28 AM UTC 24 Oct 12 12:42:31 AM UTC 24 58218773 ps
T746 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_global_esc.1541707250 Oct 12 12:42:29 AM UTC 24 Oct 12 12:42:31 AM UTC 24 28074204 ps
T747 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_smoke.3015070708 Oct 12 12:42:29 AM UTC 24 Oct 12 12:42:31 AM UTC 24 33628421 ps
T748 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_sec_cm_ctrl_config_regwen.3499455958 Oct 12 12:42:42 AM UTC 24 Oct 12 12:42:45 AM UTC 24 174867207 ps
T749 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_stress_all.381031167 Oct 12 12:42:42 AM UTC 24 Oct 12 12:42:47 AM UTC 24 1112107044 ps
T750 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_glitch.2085566201 Oct 12 12:42:29 AM UTC 24 Oct 12 12:42:31 AM UTC 24 54576811 ps
T751 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_reset_invalid.601884036 Oct 12 12:42:29 AM UTC 24 Oct 12 12:42:31 AM UTC 24 351899966 ps
T752 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_disable_rom_integrity_check.1458774853 Oct 12 12:42:29 AM UTC 24 Oct 12 12:42:31 AM UTC 24 63087652 ps
T753 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_stress_all.997527839 Oct 12 12:42:43 AM UTC 24 Oct 12 12:42:47 AM UTC 24 2889834607 ps
T754 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_sec_cm_ctrl_config_regwen.1819242920 Oct 12 12:42:29 AM UTC 24 Oct 12 12:42:31 AM UTC 24 115881039 ps
T755 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_escalation_timeout.1198831863 Oct 12 12:42:29 AM UTC 24 Oct 12 12:42:31 AM UTC 24 150321162 ps
T756 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_lowpower_invalid.359483365 Oct 12 12:42:29 AM UTC 24 Oct 12 12:42:31 AM UTC 24 47051626 ps
T757 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_aborted_low_power.2090761833 Oct 12 12:42:29 AM UTC 24 Oct 12 12:42:31 AM UTC 24 80872426 ps
T758 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_reset.3607163628 Oct 12 12:42:29 AM UTC 24 Oct 12 12:42:31 AM UTC 24 36829114 ps
T759 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_esc_clk_rst_malfunc.1919362322 Oct 12 12:42:29 AM UTC 24 Oct 12 12:42:32 AM UTC 24 30872596 ps
T760 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_lowpower_wakeup_race.3147467975 Oct 12 12:42:29 AM UTC 24 Oct 12 12:42:32 AM UTC 24 134658032 ps
T761 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_sec_cm_rstmgr_intersig_mubi.3147855492 Oct 12 12:42:29 AM UTC 24 Oct 12 12:42:32 AM UTC 24 76630661 ps
T762 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_global_esc.206890485 Oct 12 12:42:29 AM UTC 24 Oct 12 12:42:32 AM UTC 24 57376781 ps
T763 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_sec_cm_ctrl_config_regwen.3431172623 Oct 12 12:42:29 AM UTC 24 Oct 12 12:42:32 AM UTC 24 26684671 ps
T764 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_wakeup.15903509 Oct 12 12:42:29 AM UTC 24 Oct 12 12:42:32 AM UTC 24 191561222 ps
T765 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_wakeup_reset.263789133 Oct 12 12:42:29 AM UTC 24 Oct 12 12:42:32 AM UTC 24 343138294 ps
T70 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_stress_all_with_rand_reset.4048274156 Oct 12 12:42:42 AM UTC 24 Oct 12 12:42:48 AM UTC 24 2823496202 ps
T766 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.599220056 Oct 12 12:42:28 AM UTC 24 Oct 12 12:42:32 AM UTC 24 1283767101 ps
T767 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2143047515 Oct 12 12:42:28 AM UTC 24 Oct 12 12:42:32 AM UTC 24 1075789442 ps
T768 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2145271624 Oct 12 12:42:29 AM UTC 24 Oct 12 12:42:34 AM UTC 24 932136443 ps
T769 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3252555455 Oct 12 12:42:29 AM UTC 24 Oct 12 12:42:34 AM UTC 24 825034537 ps
T770 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_stress_all.2990026856 Oct 12 12:42:29 AM UTC 24 Oct 12 12:42:34 AM UTC 24 7930480582 ps
T771 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_stress_all_with_rand_reset.2342152439 Oct 12 12:42:29 AM UTC 24 Oct 12 12:42:38 AM UTC 24 2120859586 ps
T772 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_glitch.2365856270 Oct 12 12:42:42 AM UTC 24 Oct 12 12:42:43 AM UTC 24 51857374 ps
T773 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_wakeup.604456761 Oct 12 12:42:54 AM UTC 24 Oct 12 12:42:56 AM UTC 24 113713239 ps
T774 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_escalation_timeout.2039768020 Oct 12 12:42:42 AM UTC 24 Oct 12 12:42:43 AM UTC 24 351737094 ps
T775 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_disable_rom_integrity_check.204745256 Oct 12 12:42:42 AM UTC 24 Oct 12 12:42:44 AM UTC 24 89207089 ps
T776 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_smoke.1171983622 Oct 12 12:42:42 AM UTC 24 Oct 12 12:42:44 AM UTC 24 60572458 ps
T777 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_lowpower_invalid.2831701376 Oct 12 12:42:42 AM UTC 24 Oct 12 12:42:44 AM UTC 24 43144298 ps
T778 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_reset_invalid.328273077 Oct 12 12:42:42 AM UTC 24 Oct 12 12:42:44 AM UTC 24 114385454 ps
T779 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_wakeup.2577136552 Oct 12 12:42:42 AM UTC 24 Oct 12 12:42:44 AM UTC 24 101069414 ps
T780 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_esc_clk_rst_malfunc.4042306391 Oct 12 12:42:42 AM UTC 24 Oct 12 12:42:44 AM UTC 24 31787921 ps
T781 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_global_esc.2774421749 Oct 12 12:42:55 AM UTC 24 Oct 12 12:42:56 AM UTC 24 68262224 ps
T782 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_reset.3902956147 Oct 12 12:42:42 AM UTC 24 Oct 12 12:42:44 AM UTC 24 72110938 ps
T783 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3848840867 Oct 12 12:42:42 AM UTC 24 Oct 12 12:42:47 AM UTC 24 779532088 ps
T784 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_global_esc.477964709 Oct 12 12:42:42 AM UTC 24 Oct 12 12:42:44 AM UTC 24 34172329 ps
T785 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_aborted_low_power.1640665358 Oct 12 12:42:42 AM UTC 24 Oct 12 12:42:44 AM UTC 24 79790931 ps
T786 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_sec_cm_rstmgr_intersig_mubi.1997747208 Oct 12 12:42:42 AM UTC 24 Oct 12 12:42:44 AM UTC 24 170068996 ps
T787 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_glitch.834029706 Oct 12 12:42:42 AM UTC 24 Oct 12 12:42:44 AM UTC 24 47063719 ps
T788 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_lowpower_wakeup_race.756861240 Oct 12 12:42:42 AM UTC 24 Oct 12 12:42:44 AM UTC 24 302158013 ps
T789 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_wakeup_reset.2158673450 Oct 12 12:42:42 AM UTC 24 Oct 12 12:42:44 AM UTC 24 174318002 ps
T790 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_escalation_timeout.1122989321 Oct 12 12:42:42 AM UTC 24 Oct 12 12:42:44 AM UTC 24 928462762 ps
T791 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_disable_rom_integrity_check.1352513969 Oct 12 12:42:42 AM UTC 24 Oct 12 12:42:44 AM UTC 24 71318311 ps
T792 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_reset.1845298763 Oct 12 12:42:43 AM UTC 24 Oct 12 12:42:45 AM UTC 24 42309485 ps
T793 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_lowpower_invalid.150569506 Oct 12 12:42:42 AM UTC 24 Oct 12 12:42:45 AM UTC 24 54185239 ps
T794 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_smoke.3276078123 Oct 12 12:42:43 AM UTC 24 Oct 12 12:42:45 AM UTC 24 39816904 ps
T795 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_reset_invalid.43112322 Oct 12 12:42:42 AM UTC 24 Oct 12 12:42:45 AM UTC 24 101675923 ps
T796 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.518017051 Oct 12 12:42:42 AM UTC 24 Oct 12 12:42:47 AM UTC 24 856121292 ps
T797 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_ctrl_config_regwen.2510500610 Oct 12 12:43:22 AM UTC 24 Oct 12 12:43:25 AM UTC 24 394873818 ps
T798 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_lowpower_wakeup_race.796879088 Oct 12 12:42:54 AM UTC 24 Oct 12 12:42:56 AM UTC 24 414122608 ps
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