Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32104

1

T1

2

T3

2

T4

4

auto[1]

30480

1

T3

2

T4

4

T5

10

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32174

1

T1

2

T4

2

T5

8

auto[1]

30410

1

T3

4

T4

6

T5

20

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30773

1

T3

4

T4

8

T5

14

auto[1]

31811

1

T1

2

T5

14

T8

7

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35216

1

T1

1

T3

2

T4

4

auto[1]

27368

1

T1

1

T3

2

T4

4

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30803

1

T4

6

T5

12

T8

9

auto[1]

31781

1

T1

2

T3

4

T4

2

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31871

1

T1

2

T3

4

T4

2

auto[1]

30713

1

T4

6

T5

16

T8

10

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1087

1

T8

1

T14

3

T38

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

832

1

T14

3

T38

1

T79

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1073

1

T38

1

T40

1

T79

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

838

1

T38

1

T79

1

T81

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1066

1

T14

2

T38

2

T60

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

816

1

T14

2

T38

2

T79

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1803

1

T1

1

T5

1

T8

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1541

1

T1

1

T5

1

T9

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1133

1

T4

1

T9

1

T14

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

915

1

T4

1

T14

3

T38

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1118

1

T5

1

T14

2

T38

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

881

1

T5

1

T14

2

T38

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1065

1

T5

1

T14

2

T38

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

817

1

T5

1

T14

2

T38

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1091

1

T8

1

T14

4

T38

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

843

1

T14

4

T38

4

T15

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1114

1

T9

1

T38

1

T32

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

883

1

T9

1

T38

1

T32

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1059

1

T5

1

T14

3

T38

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

818

1

T5

1

T14

3

T38

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1035

1

T3

1

T5

1

T14

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

816

1

T3

1

T5

1

T14

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1060

1

T38

3

T15

1

T60

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

817

1

T38

3

T172

3

T82

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1052

1

T4

1

T5

1

T38

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

818

1

T4

1

T5

1

T38

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1073

1

T14

2

T38

2

T15

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

819

1

T14

2

T38

2

T15

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1105

1

T5

1

T38

1

T34

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

837

1

T5

1

T38

1

T34

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1070

1

T5

2

T8

1

T9

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

809

1

T5

2

T9

1

T14

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1113

1

T14

2

T60

1

T79

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

872

1

T14

2

T60

1

T79

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1108

1

T8

1

T38

3

T15

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

854

1

T38

3

T15

1

T33

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1087

1

T8

2

T14

2

T40

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

848

1

T14

2

T40

1

T15

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1033

1

T14

1

T38

1

T15

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

803

1

T14

1

T38

1

T15

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1042

1

T8

1

T14

2

T38

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

798

1

T14

2

T38

1

T33

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1075

1

T8

1

T9

1

T14

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

815

1

T9

1

T14

2

T38

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1090

1

T8

2

T14

2

T38

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

822

1

T14

2

T38

2

T33

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1062

1

T5

1

T8

1

T34

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

833

1

T5

1

T34

1

T60

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1076

1

T5

2

T8

3

T16

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

837

1

T5

2

T79

1

T185

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1042

1

T5

1

T38

1

T34

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

806

1

T5

1

T38

1

T34

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1071

1

T3

1

T4

1

T14

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

804

1

T3

1

T4

1

T14

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1062

1

T14

1

T38

1

T60

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

797

1

T14

1

T38

1

T79

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1094

1

T4

1

T8

1

T14

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

877

1

T4

1

T14

3

T79

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1068

1

T8

1

T14

3

T15

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

813

1

T14

3

T33

1

T79

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1090

1

T5

1

T8

1

T14

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

861

1

T5

1

T14

1

T38

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1099

1

T14

2

T38

1

T15

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

828

1

T14

2

T38

1

T15

1