Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24643

1

T1

2

T3

16

T4

14

auto[1]

23657

1

T3

22

T4

22

T5

2

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24548

1

T1

2

T3

16

T4

12

auto[1]

23752

1

T3

22

T4

24

T5

2

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23644

1

T3

22

T4

18

T5

2

auto[1]

24656

1

T1

2

T3

16

T4

18

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26989

1

T1

1

T3

19

T4

18

auto[1]

21311

1

T1

1

T3

19

T4

18

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23593

1

T3

26

T4

16

T6

7

auto[1]

24707

1

T1

2

T3

12

T4

20

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24589

1

T1

2

T3

14

T4

18

auto[1]

23711

1

T3

24

T4

18

T5

4

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

869

1

T3

2

T8

4

T37

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

693

1

T3

2

T8

4

T37

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

804

1

T4

1

T8

2

T10

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

614

1

T4

1

T8

2

T10

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

772

1

T8

2

T10

1

T37

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

585

1

T8

2

T37

2

T16

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1322

1

T1

1

T4

1

T8

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1144

1

T1

1

T4

1

T8

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

802

1

T8

1

T37

1

T40

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

630

1

T8

1

T37

1

T40

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

788

1

T3

1

T8

3

T10

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

639

1

T3

1

T8

3

T10

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

820

1

T37

2

T35

3

T16

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

645

1

T37

2

T35

3

T16

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

898

1

T4

1

T10

2

T37

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

721

1

T4

1

T10

1

T37

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

811

1

T3

1

T6

1

T8

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

665

1

T3

1

T8

2

T37

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

847

1

T4

1

T10

2

T37

5

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

678

1

T4

1

T10

1

T37

5

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

815

1

T4

1

T8

4

T10

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

651

1

T4

1

T8

4

T10

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

840

1

T6

1

T8

1

T10

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

658

1

T8

1

T10

1

T16

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

850

1

T3

1

T6

1

T8

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

675

1

T3

1

T8

1

T37

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

806

1

T8

1

T10

1

T37

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

618

1

T8

1

T37

1

T33

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

842

1

T3

3

T4

1

T6

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

657

1

T3

3

T4

1

T8

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

832

1

T4

1

T5

1

T6

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

652

1

T4

1

T5

1

T8

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

850

1

T6

2

T10

1

T37

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

673

1

T37

1

T35

1

T16

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

869

1

T3

2

T8

2

T10

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

672

1

T3

2

T8

2

T37

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

819

1

T8

2

T10

1

T37

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

644

1

T8

2

T37

4

T16

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

839

1

T8

2

T10

1

T40

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

649

1

T8

2

T40

1

T33

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

779

1

T4

1

T8

2

T10

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

616

1

T4

1

T8

2

T10

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

813

1

T4

1

T40

1

T16

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

627

1

T4

1

T23

2

T26

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

792

1

T3

2

T4

1

T5

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

630

1

T3

2

T4

1

T5

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

842

1

T3

1

T8

1

T10

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

688

1

T3

1

T8

1

T10

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

833

1

T3

1

T4

1

T37

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

650

1

T3

1

T4

1

T37

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

802

1

T3

1

T4

2

T6

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

625

1

T3

1

T4

2

T8

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

841

1

T4

2

T8

1

T37

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

658

1

T4

2

T8

1

T37

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

795

1

T8

1

T10

1

T37

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

602

1

T8

1

T37

2

T33

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

856

1

T3

1

T4

1

T6

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

692

1

T3

1

T4

1

T8

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

819

1

T3

3

T8

1

T10

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

628

1

T3

3

T8

1

T10

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

852

1

T4

1

T8

2

T37

7

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

677

1

T4

1

T8

2

T37

7

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

870

1

T4

1

T8

3

T37

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

655

1

T4

1

T8

3

T37

2