Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.95 98.23 96.58 99.44 96.00 96.37 100.00 99.02


Total tests in report: 1119
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
80.27 80.27 95.74 95.74 86.02 86.02 83.46 83.46 60.00 60.00 92.56 92.56 90.79 90.79 53.36 53.36 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_wakeup_reset.2979780305
85.01 4.74 96.14 0.40 86.31 0.29 86.75 3.29 82.00 22.00 93.13 0.57 91.84 1.05 58.92 5.56 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_reset_invalid.1611411768
88.06 3.05 96.79 0.64 86.88 0.57 86.94 0.19 86.00 4.00 93.70 0.57 92.63 0.79 73.49 14.57 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_stress_all.1172453987
90.21 2.15 96.95 0.16 88.02 1.14 96.52 9.59 88.00 2.00 94.47 0.76 93.68 1.05 73.81 0.33 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm.175581972
91.95 1.74 96.95 0.00 88.30 0.29 98.03 1.50 88.00 0.00 94.47 0.00 93.95 0.26 83.96 10.15 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2815018880
93.46 1.51 97.27 0.32 90.87 2.57 98.78 0.75 88.00 0.00 94.66 0.19 95.26 1.32 89.36 5.40 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_stress_all_with_rand_reset.643249170
94.76 1.30 97.83 0.56 93.87 3.00 98.97 0.19 88.00 0.00 95.42 0.76 96.58 1.32 92.64 3.27 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.504057679
95.90 1.14 97.83 0.00 93.87 0.00 98.97 0.00 96.00 8.00 95.42 0.00 96.58 0.00 92.64 0.00 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_lowpower_invalid.623191150
96.21 0.31 98.07 0.24 94.01 0.14 98.97 0.00 96.00 0.00 95.42 0.00 96.58 0.00 94.44 1.80 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_intr_test.2885248141
96.50 0.29 98.07 0.00 94.15 0.14 98.97 0.00 96.00 0.00 95.42 0.00 96.84 0.26 96.07 1.64 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_ctrl_config_regwen.3576241416
96.77 0.27 98.23 0.16 94.58 0.43 98.97 0.00 96.00 0.00 96.18 0.76 97.37 0.53 96.07 0.00 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_escalation_timeout.4104001944
97.03 0.26 98.23 0.00 94.58 0.00 98.97 0.00 96.00 0.00 96.18 0.00 99.21 1.84 96.07 0.00 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_rw.535163161
97.24 0.21 98.23 0.00 95.86 1.28 98.97 0.00 96.00 0.00 96.18 0.00 99.21 0.00 96.24 0.16 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_tl_errors.3118733124
97.40 0.16 98.23 0.00 95.86 0.00 98.97 0.00 96.00 0.00 96.37 0.19 99.47 0.26 96.89 0.65 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_disable_rom_integrity_check.872982666
97.55 0.15 98.23 0.00 96.01 0.14 99.44 0.47 96.00 0.00 96.37 0.00 99.74 0.26 97.05 0.16 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_aborted_low_power.452882707
97.64 0.09 98.23 0.00 96.15 0.14 99.44 0.00 96.00 0.00 96.37 0.00 99.74 0.00 97.55 0.49 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.316024620
97.69 0.05 98.23 0.00 96.15 0.00 99.44 0.00 96.00 0.00 96.37 0.00 99.74 0.00 97.87 0.33 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_intr_test.462882686
97.73 0.05 98.23 0.00 96.15 0.00 99.44 0.00 96.00 0.00 96.37 0.00 99.74 0.00 98.20 0.33 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.782028111
97.78 0.05 98.23 0.00 96.15 0.00 99.44 0.00 96.00 0.00 96.37 0.00 99.74 0.00 98.53 0.33 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_stress_all.3963635269
97.83 0.05 98.23 0.00 96.15 0.00 99.44 0.00 96.00 0.00 96.37 0.00 99.74 0.00 98.85 0.33 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_disable_rom_integrity_check.4102155260
97.85 0.02 98.23 0.00 96.15 0.00 99.44 0.00 96.00 0.00 96.37 0.00 99.74 0.00 99.02 0.16 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_disable_rom_integrity_check.2036951578
97.87 0.02 98.23 0.00 96.29 0.14 99.44 0.00 96.00 0.00 96.37 0.00 99.74 0.00 99.02 0.00 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_tl_errors.320155180
97.89 0.02 98.23 0.00 96.43 0.14 99.44 0.00 96.00 0.00 96.37 0.00 99.74 0.00 99.02 0.00 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.412202331
97.91 0.02 98.23 0.00 96.58 0.14 99.44 0.00 96.00 0.00 96.37 0.00 99.74 0.00 99.02 0.00 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_glitch.2157180450


Tests that do not contribute to grading

Name   
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.3513931804
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.3346109123
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.3632372615
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.1738363186
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_rw.3327182573
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.2727780035
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_tl_errors.592512922
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.4021461716
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.1782613000
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.868068250
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.1071944306
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.529244003
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_rw.1911303951
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.2218256181
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.1956276198
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_csr_rw.986850354
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_intr_test.4154341126
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.789645017
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_tl_errors.3093420949
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.1876097787
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.3163036203
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_csr_rw.1459903553
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_intr_test.795429349
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.1045695215
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_tl_errors.3156295604
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.1743666630
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.2099949622
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_csr_rw.1323128780
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_intr_test.2378417036
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.3289568640
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_tl_errors.1638887138
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.3702183937
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.650673108
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_csr_rw.2772029897
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_intr_test.1383691218
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.1043638173
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_tl_errors.1053423344
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.1658107323
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.611195012
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_csr_rw.1052940607
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_intr_test.2658870682
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.2299354270
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_tl_errors.2772612882
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.241360081
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_csr_rw.3872240100
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_intr_test.580378321
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.591438712
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_tl_errors.1975252177
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.2552615161
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.3708831797
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_csr_rw.3942278158
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_intr_test.2405121555
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.474564350
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_tl_errors.2166462532
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.3954287785
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.817281469
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_csr_rw.97186805
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_intr_test.1757997122
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.3412240725
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_tl_errors.4186761872
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.192183375
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.3184355648
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_csr_rw.3008528571
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_intr_test.1927192387
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.2398449690
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_tl_errors.564578544
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.633688972
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.3151283994
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_csr_rw.158125257
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_intr_test.3321309210
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.1910544750
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_tl_errors.2818516858
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.4217932472
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.695185686
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.3793869915
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.1405764395
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.1922180718
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_rw.3975537135
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_intr_test.2909671775
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.1842251601
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_tl_errors.1735943805
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.543799887
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/20.pwrmgr_intr_test.1231035363
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/21.pwrmgr_intr_test.2011277704
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/22.pwrmgr_intr_test.1641909671
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/23.pwrmgr_intr_test.4197672907
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/24.pwrmgr_intr_test.1675590272
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/25.pwrmgr_intr_test.2314307908
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/26.pwrmgr_intr_test.243302915
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/27.pwrmgr_intr_test.2344241931
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/28.pwrmgr_intr_test.1120358723
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/29.pwrmgr_intr_test.2208039654
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.1423936259
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.4216984996
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.943113994
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.4050411281
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_intr_test.1918591669
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.2022801213
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_tl_errors.3656020522
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/30.pwrmgr_intr_test.3495466528
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/31.pwrmgr_intr_test.66989386
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/32.pwrmgr_intr_test.548020927
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/33.pwrmgr_intr_test.3241756550
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/34.pwrmgr_intr_test.848098780
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/35.pwrmgr_intr_test.1094699863
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/36.pwrmgr_intr_test.3076189370
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/37.pwrmgr_intr_test.891402559
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/38.pwrmgr_intr_test.1586171289
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/39.pwrmgr_intr_test.2390854245
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.3434181594
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.1701974003
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/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_glitch.3726070369
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/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_lowpower_invalid.225993902
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/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_reset.3635334824
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_reset_invalid.1872759006
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_ctrl_config_regwen.1531402903
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.743461578
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.566084587
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_rstmgr_intersig_mubi.925008009
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/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_aborted_low_power.3489191258
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_disable_rom_integrity_check.1363190905
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/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_global_esc.82345093
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_lowpower_invalid.4177150938
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/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_reset_invalid.1483397025
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_ctrl_config_regwen.3872601346
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.223085253
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1572920478
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_rstmgr_intersig_mubi.927290990
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/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_stress_all.719824477
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_stress_all_with_rand_reset.3666969766
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_wakeup.4107153801
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_wakeup_reset.4232960467
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_aborted_low_power.2848599806
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_disable_rom_integrity_check.4235442442
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_esc_clk_rst_malfunc.2022749816
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_escalation_timeout.776150929
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_glitch.294749007
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_global_esc.2804208025
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_lowpower_invalid.2696647132
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_lowpower_wakeup_race.1485114644
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset.2660063120
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset_invalid.1349122751
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_ctrl_config_regwen.1313808325
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.945525553
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3172464158
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_rstmgr_intersig_mubi.3797391772
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_smoke.413589541
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_stress_all.2172366844
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_stress_all_with_rand_reset.914221412
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_wakeup.4007702395
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_wakeup_reset.3033425179
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_aborted_low_power.1421599473
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_disable_rom_integrity_check.142912001
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.4174546900
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_escalation_timeout.2719507607
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_glitch.3745099788
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_global_esc.1465896777
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_lowpower_invalid.969723563
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_lowpower_wakeup_race.2196402834
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset.9337180
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/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_ctrl_config_regwen.37840218
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1997111464
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3745637175
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.319300767
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/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_wakeup_reset.725631751
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_aborted_low_power.2308903693
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_disable_rom_integrity_check.2783417983
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_esc_clk_rst_malfunc.1007274409
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_escalation_timeout.4078780533
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_glitch.1802174749
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_global_esc.1888682800
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_lowpower_invalid.217036869
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_lowpower_wakeup_race.1887925475
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset.2702721606
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset_invalid.1372526582
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_ctrl_config_regwen.3274695947
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3184257990
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2083471909
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rstmgr_intersig_mubi.3859753356
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_smoke.2666996103
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_stress_all.666967873
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_stress_all_with_rand_reset.1493896694
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup.3060037557
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup_reset.4254047362




Total test records in report: 1119
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html

TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_smoke.3538623448 Feb 09 02:03:35 PM UTC 25 Feb 09 02:03:37 PM UTC 25 31037247 ps
T2 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_reset.2846809536 Feb 09 02:03:35 PM UTC 25 Feb 09 02:03:37 PM UTC 25 56946259 ps
T3 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_wakeup.3922965805 Feb 09 02:03:36 PM UTC 25 Feb 09 02:03:38 PM UTC 25 62772849 ps
T4 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_lowpower_wakeup_race.4063869971 Feb 09 02:03:36 PM UTC 25 Feb 09 02:03:38 PM UTC 25 105708401 ps
T5 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_wakeup_reset.2979780305 Feb 09 02:03:36 PM UTC 25 Feb 09 02:03:38 PM UTC 25 311769473 ps
T6 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_esc_clk_rst_malfunc.2954169156 Feb 09 02:03:37 PM UTC 25 Feb 09 02:03:39 PM UTC 25 31170936 ps
T7 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_rstmgr_intersig_mubi.2665365610 Feb 09 02:03:37 PM UTC 25 Feb 09 02:03:40 PM UTC 25 223308536 ps
T8 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_aborted_low_power.1298160342 Feb 09 02:03:37 PM UTC 25 Feb 09 02:03:40 PM UTC 25 50139319 ps
T9 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_ctrl_config_regwen.2611703877 Feb 09 02:03:37 PM UTC 25 Feb 09 02:03:40 PM UTC 25 68877923 ps
T10 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_global_esc.1214510512 Feb 09 02:03:38 PM UTC 25 Feb 09 02:03:41 PM UTC 25 90423524 ps
T13 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_disable_rom_integrity_check.3957984190 Feb 09 02:03:38 PM UTC 25 Feb 09 02:03:41 PM UTC 25 76134668 ps
T20 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_glitch.995767344 Feb 09 02:03:38 PM UTC 25 Feb 09 02:03:41 PM UTC 25 34324211 ps
T11 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_escalation_timeout.4104001944 Feb 09 02:03:38 PM UTC 25 Feb 09 02:03:41 PM UTC 25 1266022400 ps
T14 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1123430134 Feb 09 02:03:37 PM UTC 25 Feb 09 02:03:41 PM UTC 25 946383901 ps
T38 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.532732470 Feb 09 02:03:37 PM UTC 25 Feb 09 02:03:41 PM UTC 25 1302657691 ps
T29 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_reset_invalid.1611411768 Feb 09 02:03:39 PM UTC 25 Feb 09 02:03:42 PM UTC 25 101029283 ps
T40 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_lowpower_invalid.623191150 Feb 09 02:03:40 PM UTC 25 Feb 09 02:03:42 PM UTC 25 45711843 ps
T78 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_smoke.1525466466 Feb 09 02:03:40 PM UTC 25 Feb 09 02:03:42 PM UTC 25 62570939 ps
T15 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_stress_all.1172453987 Feb 09 02:03:40 PM UTC 25 Feb 09 02:03:43 PM UTC 25 530270203 ps
T21 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm.2332610423 Feb 09 02:03:40 PM UTC 25 Feb 09 02:03:43 PM UTC 25 435130942 ps
T32 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_wakeup.1334228834 Feb 09 02:03:41 PM UTC 25 Feb 09 02:03:43 PM UTC 25 148935955 ps
T16 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_aborted_low_power.1758678613 Feb 09 02:03:41 PM UTC 25 Feb 09 02:03:44 PM UTC 25 56912031 ps
T33 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_wakeup_reset.910479121 Feb 09 02:03:41 PM UTC 25 Feb 09 02:03:44 PM UTC 25 184649477 ps
T34 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_lowpower_wakeup_race.3822793692 Feb 09 02:03:41 PM UTC 25 Feb 09 02:03:44 PM UTC 25 200307049 ps
T35 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_reset.274360160 Feb 09 02:03:41 PM UTC 25 Feb 09 02:03:44 PM UTC 25 44638761 ps
T36 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_rstmgr_intersig_mubi.30362371 Feb 09 02:03:41 PM UTC 25 Feb 09 02:03:44 PM UTC 25 90020352 ps
T12 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_esc_clk_rst_malfunc.1167997986 Feb 09 02:03:43 PM UTC 25 Feb 09 02:03:45 PM UTC 25 30847823 ps
T37 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_global_esc.2571620752 Feb 09 02:03:43 PM UTC 25 Feb 09 02:03:45 PM UTC 25 39486365 ps
T28 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_disable_rom_integrity_check.3382634264 Feb 09 02:03:43 PM UTC 25 Feb 09 02:03:45 PM UTC 25 69069805 ps
T60 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_ctrl_config_regwen.3523396928 Feb 09 02:03:43 PM UTC 25 Feb 09 02:03:45 PM UTC 25 141197827 ps
T17 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_glitch.2157180450 Feb 09 02:03:43 PM UTC 25 Feb 09 02:03:45 PM UTC 25 39981765 ps
T39 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_reset_invalid.4201510042 Feb 09 02:03:43 PM UTC 25 Feb 09 02:03:46 PM UTC 25 124134458 ps
T79 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2815018880 Feb 09 02:03:41 PM UTC 25 Feb 09 02:03:46 PM UTC 25 787760899 ps
T157 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_escalation_timeout.3002474935 Feb 09 02:03:43 PM UTC 25 Feb 09 02:03:46 PM UTC 25 827519438 ps
T27 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_stress_all.464173947 Feb 09 02:03:44 PM UTC 25 Feb 09 02:03:46 PM UTC 25 73747382 ps
T44 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_lowpower_invalid.4274698941 Feb 09 02:03:44 PM UTC 25 Feb 09 02:03:46 PM UTC 25 112080660 ps
T80 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_smoke.2075951473 Feb 09 02:03:44 PM UTC 25 Feb 09 02:03:46 PM UTC 25 60991991 ps
T22 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm.175581972 Feb 09 02:03:44 PM UTC 25 Feb 09 02:03:47 PM UTC 25 457248952 ps
T81 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_lowpower_wakeup_race.2030353262 Feb 09 02:03:45 PM UTC 25 Feb 09 02:03:48 PM UTC 25 201861729 ps
T140 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_reset.2145193326 Feb 09 02:03:45 PM UTC 25 Feb 09 02:03:48 PM UTC 25 393907625 ps
T172 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1207540554 Feb 09 02:03:41 PM UTC 25 Feb 09 02:03:48 PM UTC 25 946125705 ps
T41 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_aborted_low_power.2540997402 Feb 09 02:03:46 PM UTC 25 Feb 09 02:03:48 PM UTC 25 33382757 ps
T185 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_wakeup.2215377566 Feb 09 02:03:45 PM UTC 25 Feb 09 02:03:48 PM UTC 25 298615096 ps
T82 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_wakeup_reset.2239509069 Feb 09 02:03:45 PM UTC 25 Feb 09 02:03:49 PM UTC 25 474526222 ps
T141 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_rstmgr_intersig_mubi.3717072240 Feb 09 02:03:47 PM UTC 25 Feb 09 02:03:49 PM UTC 25 72594085 ps
T195 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_global_esc.1315416534 Feb 09 02:03:47 PM UTC 25 Feb 09 02:03:49 PM UTC 25 90906653 ps
T165 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_esc_clk_rst_malfunc.2206956952 Feb 09 02:03:47 PM UTC 25 Feb 09 02:03:49 PM UTC 25 30811460 ps
T18 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_glitch.1767425806 Feb 09 02:03:47 PM UTC 25 Feb 09 02:03:49 PM UTC 25 57293590 ps
T61 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_ctrl_config_regwen.3576241416 Feb 09 02:03:47 PM UTC 25 Feb 09 02:03:50 PM UTC 25 168385216 ps
T158 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_escalation_timeout.1702639889 Feb 09 02:03:47 PM UTC 25 Feb 09 02:03:50 PM UTC 25 749901906 ps
T167 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_disable_rom_integrity_check.661045559 Feb 09 02:03:48 PM UTC 25 Feb 09 02:03:50 PM UTC 25 126257385 ps
T43 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_reset_invalid.285729068 Feb 09 02:03:48 PM UTC 25 Feb 09 02:03:50 PM UTC 25 93121915 ps
T64 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.203112191 Feb 09 02:03:47 PM UTC 25 Feb 09 02:03:51 PM UTC 25 1052808608 ps
T173 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.972119048 Feb 09 02:03:47 PM UTC 25 Feb 09 02:03:51 PM UTC 25 875904050 ps
T45 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_lowpower_invalid.1861561363 Feb 09 02:03:49 PM UTC 25 Feb 09 02:03:51 PM UTC 25 47872648 ps
T196 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_smoke.2728378119 Feb 09 02:03:49 PM UTC 25 Feb 09 02:03:52 PM UTC 25 27669750 ps
T197 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_global_esc.3837801029 Feb 09 02:03:52 PM UTC 25 Feb 09 02:03:54 PM UTC 25 48950372 ps
T198 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_reset.2987632851 Feb 09 02:03:49 PM UTC 25 Feb 09 02:03:52 PM UTC 25 67988369 ps
T83 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_lowpower_wakeup_race.914469203 Feb 09 02:03:49 PM UTC 25 Feb 09 02:03:52 PM UTC 25 124620069 ps
T199 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_wakeup.2184924051 Feb 09 02:03:50 PM UTC 25 Feb 09 02:03:52 PM UTC 25 210535906 ps
T23 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm.800694571 Feb 09 02:03:49 PM UTC 25 Feb 09 02:03:52 PM UTC 25 1614924679 ps
T42 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_aborted_low_power.452882707 Feb 09 02:03:51 PM UTC 25 Feb 09 02:03:53 PM UTC 25 159670063 ps
T200 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_rstmgr_intersig_mubi.1894003383 Feb 09 02:03:51 PM UTC 25 Feb 09 02:03:53 PM UTC 25 152890121 ps
T201 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_wakeup_reset.251405389 Feb 09 02:03:51 PM UTC 25 Feb 09 02:03:54 PM UTC 25 164582505 ps
T129 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_stress_all.3963635269 Feb 09 02:03:49 PM UTC 25 Feb 09 02:03:54 PM UTC 25 1190525883 ps
T166 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_esc_clk_rst_malfunc.4226502078 Feb 09 02:03:52 PM UTC 25 Feb 09 02:03:54 PM UTC 25 28533832 ps
T19 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_glitch.3488547498 Feb 09 02:03:52 PM UTC 25 Feb 09 02:03:54 PM UTC 25 35574682 ps
T168 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1440856491 Feb 09 02:03:51 PM UTC 25 Feb 09 02:03:54 PM UTC 25 1507897970 ps
T159 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_escalation_timeout.3515272582 Feb 09 02:03:52 PM UTC 25 Feb 09 02:03:55 PM UTC 25 185385149 ps
T202 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_ctrl_config_regwen.1747254735 Feb 09 02:03:52 PM UTC 25 Feb 09 02:03:55 PM UTC 25 170520640 ps
T174 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2947552864 Feb 09 02:03:51 PM UTC 25 Feb 09 02:03:55 PM UTC 25 747700327 ps
T203 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_reset_invalid.579526664 Feb 09 02:03:53 PM UTC 25 Feb 09 02:03:56 PM UTC 25 147421529 ps
T204 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_lowpower_invalid.3142376640 Feb 09 02:03:53 PM UTC 25 Feb 09 02:03:56 PM UTC 25 47973014 ps
T169 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_disable_rom_integrity_check.2377861012 Feb 09 02:03:53 PM UTC 25 Feb 09 02:03:56 PM UTC 25 61144138 ps
T30 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm.2059071772 Feb 09 02:03:53 PM UTC 25 Feb 09 02:03:56 PM UTC 25 1097282156 ps
T205 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_smoke.1769136412 Feb 09 02:03:55 PM UTC 25 Feb 09 02:03:57 PM UTC 25 41884168 ps
T206 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_wakeup_reset.3703185680 Feb 09 02:03:55 PM UTC 25 Feb 09 02:03:57 PM UTC 25 208767910 ps
T207 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_reset.3553602008 Feb 09 02:03:55 PM UTC 25 Feb 09 02:03:57 PM UTC 25 99788573 ps
T208 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_wakeup.912998740 Feb 09 02:03:55 PM UTC 25 Feb 09 02:03:57 PM UTC 25 148641623 ps
T107 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_aborted_low_power.1711920600 Feb 09 02:03:55 PM UTC 25 Feb 09 02:03:57 PM UTC 25 42158220 ps
T209 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_lowpower_wakeup_race.4016412452 Feb 09 02:03:55 PM UTC 25 Feb 09 02:03:57 PM UTC 25 216574209 ps
T160 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_esc_clk_rst_malfunc.2284042263 Feb 09 02:03:56 PM UTC 25 Feb 09 02:03:58 PM UTC 25 30794053 ps
T210 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_global_esc.103359976 Feb 09 02:03:56 PM UTC 25 Feb 09 02:03:58 PM UTC 25 233230143 ps
T211 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_ctrl_config_regwen.954912260 Feb 09 02:03:56 PM UTC 25 Feb 09 02:03:59 PM UTC 25 123775657 ps
T212 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_rstmgr_intersig_mubi.2152323756 Feb 09 02:03:56 PM UTC 25 Feb 09 02:03:59 PM UTC 25 170330528 ps
T24 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_stress_all_with_rand_reset.2524771266 Feb 09 02:03:40 PM UTC 25 Feb 09 02:03:59 PM UTC 25 5892474166 ps
T132 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_escalation_timeout.1436833449 Feb 09 02:03:56 PM UTC 25 Feb 09 02:03:59 PM UTC 25 168977353 ps
T133 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_disable_rom_integrity_check.872982666 Feb 09 02:03:57 PM UTC 25 Feb 09 02:03:59 PM UTC 25 123478203 ps
T108 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_stress_all.3142261048 Feb 09 02:03:53 PM UTC 25 Feb 09 02:04:00 PM UTC 25 2120275685 ps
T134 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_glitch.647452803 Feb 09 02:03:57 PM UTC 25 Feb 09 02:04:00 PM UTC 25 64443469 ps
T135 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_reset_invalid.192050412 Feb 09 02:03:57 PM UTC 25 Feb 09 02:04:00 PM UTC 25 130360952 ps
T136 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2276615945 Feb 09 02:03:55 PM UTC 25 Feb 09 02:04:00 PM UTC 25 749785093 ps
T137 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2970152814 Feb 09 02:03:56 PM UTC 25 Feb 09 02:04:00 PM UTC 25 2071155491 ps
T138 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_lowpower_invalid.1605677762 Feb 09 02:03:59 PM UTC 25 Feb 09 02:04:01 PM UTC 25 57066773 ps
T139 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_smoke.1183071837 Feb 09 02:03:59 PM UTC 25 Feb 09 02:04:01 PM UTC 25 33596974 ps
T213 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_reset.3635334824 Feb 09 02:03:59 PM UTC 25 Feb 09 02:04:01 PM UTC 25 73864912 ps
T31 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm.234444695 Feb 09 02:03:59 PM UTC 25 Feb 09 02:04:01 PM UTC 25 452485337 ps
T214 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset.9337180 Feb 09 02:04:13 PM UTC 25 Feb 09 02:04:16 PM UTC 25 60996397 ps
T215 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_lowpower_wakeup_race.1196924047 Feb 09 02:04:00 PM UTC 25 Feb 09 02:04:02 PM UTC 25 72530122 ps
T216 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_wakeup.2868595346 Feb 09 02:04:00 PM UTC 25 Feb 09 02:04:02 PM UTC 25 260481843 ps
T217 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_wakeup.2053032881 Feb 09 02:04:14 PM UTC 25 Feb 09 02:04:17 PM UTC 25 132300366 ps
T218 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_esc_clk_rst_malfunc.734749384 Feb 09 02:04:00 PM UTC 25 Feb 09 02:04:02 PM UTC 25 43498889 ps
T109 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_aborted_low_power.305701242 Feb 09 02:04:00 PM UTC 25 Feb 09 02:04:03 PM UTC 25 21437700 ps
T219 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_global_esc.1899411155 Feb 09 02:04:01 PM UTC 25 Feb 09 02:04:03 PM UTC 25 47725217 ps
T220 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_wakeup_reset.3589740443 Feb 09 02:04:00 PM UTC 25 Feb 09 02:04:03 PM UTC 25 415364896 ps
T221 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_stress_all.711625985 Feb 09 02:03:59 PM UTC 25 Feb 09 02:04:03 PM UTC 25 635204581 ps
T222 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_rstmgr_intersig_mubi.925008009 Feb 09 02:04:00 PM UTC 25 Feb 09 02:04:03 PM UTC 25 123270243 ps
T223 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_ctrl_config_regwen.1531402903 Feb 09 02:04:01 PM UTC 25 Feb 09 02:04:03 PM UTC 25 330280067 ps
T224 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_glitch.3726070369 Feb 09 02:04:02 PM UTC 25 Feb 09 02:04:04 PM UTC 25 74395391 ps
T225 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_reset_invalid.1872759006 Feb 09 02:04:02 PM UTC 25 Feb 09 02:04:04 PM UTC 25 308909841 ps
T226 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_lowpower_invalid.225993902 Feb 09 02:04:02 PM UTC 25 Feb 09 02:04:04 PM UTC 25 44061432 ps
T170 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_disable_rom_integrity_check.2967905957 Feb 09 02:04:02 PM UTC 25 Feb 09 02:04:05 PM UTC 25 62309390 ps
T161 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_escalation_timeout.2437073377 Feb 09 02:04:02 PM UTC 25 Feb 09 02:04:05 PM UTC 25 213473002 ps
T227 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.566084587 Feb 09 02:04:00 PM UTC 25 Feb 09 02:04:05 PM UTC 25 936123617 ps
T228 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.743461578 Feb 09 02:04:00 PM UTC 25 Feb 09 02:04:05 PM UTC 25 717595728 ps
T229 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_smoke.1087910500 Feb 09 02:04:04 PM UTC 25 Feb 09 02:04:06 PM UTC 25 40820146 ps
T230 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_reset.2824014952 Feb 09 02:04:04 PM UTC 25 Feb 09 02:04:06 PM UTC 25 97913395 ps
T231 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_wakeup_reset.4232960467 Feb 09 02:04:04 PM UTC 25 Feb 09 02:04:07 PM UTC 25 249583172 ps
T232 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_wakeup.4107153801 Feb 09 02:04:04 PM UTC 25 Feb 09 02:04:07 PM UTC 25 264182731 ps
T110 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_aborted_low_power.3489191258 Feb 09 02:04:04 PM UTC 25 Feb 09 02:04:07 PM UTC 25 70410225 ps
T233 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_lowpower_wakeup_race.962248907 Feb 09 02:04:04 PM UTC 25 Feb 09 02:04:07 PM UTC 25 264638221 ps
T162 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_esc_clk_rst_malfunc.2627187822 Feb 09 02:04:06 PM UTC 25 Feb 09 02:04:08 PM UTC 25 45280805 ps
T234 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_global_esc.82345093 Feb 09 02:04:06 PM UTC 25 Feb 09 02:04:08 PM UTC 25 23469645 ps
T235 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_ctrl_config_regwen.3872601346 Feb 09 02:04:06 PM UTC 25 Feb 09 02:04:08 PM UTC 25 122410725 ps
T236 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_glitch.3354700451 Feb 09 02:04:06 PM UTC 25 Feb 09 02:04:08 PM UTC 25 44393076 ps
T237 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_rstmgr_intersig_mubi.927290990 Feb 09 02:04:06 PM UTC 25 Feb 09 02:04:09 PM UTC 25 51752087 ps
T171 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_disable_rom_integrity_check.1363190905 Feb 09 02:04:06 PM UTC 25 Feb 09 02:04:09 PM UTC 25 59518699 ps
T163 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_escalation_timeout.2233864139 Feb 09 02:04:06 PM UTC 25 Feb 09 02:04:09 PM UTC 25 158912240 ps
T25 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_stress_all_with_rand_reset.3314611975 Feb 09 02:03:59 PM UTC 25 Feb 09 02:04:09 PM UTC 25 3861477542 ps
T194 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_lowpower_invalid.4177150938 Feb 09 02:04:08 PM UTC 25 Feb 09 02:04:10 PM UTC 25 83716289 ps
T238 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1572920478 Feb 09 02:04:04 PM UTC 25 Feb 09 02:04:10 PM UTC 25 1014798292 ps
T239 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_smoke.413589541 Feb 09 02:04:08 PM UTC 25 Feb 09 02:04:10 PM UTC 25 55969380 ps
T240 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_reset_invalid.1483397025 Feb 09 02:04:08 PM UTC 25 Feb 09 02:04:10 PM UTC 25 113680944 ps
T241 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.223085253 Feb 09 02:04:04 PM UTC 25 Feb 09 02:04:11 PM UTC 25 930022863 ps
T242 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset.2660063120 Feb 09 02:04:09 PM UTC 25 Feb 09 02:04:11 PM UTC 25 86000564 ps
T111 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_stress_all.946748259 Feb 09 02:04:04 PM UTC 25 Feb 09 02:04:11 PM UTC 25 1334676485 ps
T243 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_lowpower_wakeup_race.1485114644 Feb 09 02:04:09 PM UTC 25 Feb 09 02:04:11 PM UTC 25 248302431 ps
T244 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_wakeup.4007702395 Feb 09 02:04:09 PM UTC 25 Feb 09 02:04:11 PM UTC 25 73471304 ps
T245 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_aborted_low_power.2848599806 Feb 09 02:04:09 PM UTC 25 Feb 09 02:04:12 PM UTC 25 31613621 ps
T246 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_wakeup_reset.3033425179 Feb 09 02:04:09 PM UTC 25 Feb 09 02:04:12 PM UTC 25 247104961 ps
T164 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_esc_clk_rst_malfunc.2022749816 Feb 09 02:04:11 PM UTC 25 Feb 09 02:04:13 PM UTC 25 39834503 ps
T247 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_glitch.294749007 Feb 09 02:04:11 PM UTC 25 Feb 09 02:04:13 PM UTC 25 59755732 ps
T248 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_global_esc.2804208025 Feb 09 02:04:11 PM UTC 25 Feb 09 02:04:13 PM UTC 25 25572403 ps
T249 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_ctrl_config_regwen.1313808325 Feb 09 02:04:11 PM UTC 25 Feb 09 02:04:14 PM UTC 25 69020525 ps
T112 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_stress_all.719824477 Feb 09 02:04:08 PM UTC 25 Feb 09 02:04:14 PM UTC 25 1529237978 ps
T250 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_disable_rom_integrity_check.4235442442 Feb 09 02:04:12 PM UTC 25 Feb 09 02:04:14 PM UTC 25 62803215 ps
T251 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_rstmgr_intersig_mubi.3797391772 Feb 09 02:04:11 PM UTC 25 Feb 09 02:04:14 PM UTC 25 118386822 ps
T252 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3172464158 Feb 09 02:04:09 PM UTC 25 Feb 09 02:04:14 PM UTC 25 1194382345 ps
T253 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_escalation_timeout.776150929 Feb 09 02:04:11 PM UTC 25 Feb 09 02:04:14 PM UTC 25 621286479 ps
T254 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.945525553 Feb 09 02:04:09 PM UTC 25 Feb 09 02:04:15 PM UTC 25 933540958 ps
T255 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_lowpower_invalid.2696647132 Feb 09 02:04:13 PM UTC 25 Feb 09 02:04:15 PM UTC 25 85756272 ps
T256 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_smoke.1604198159 Feb 09 02:04:13 PM UTC 25 Feb 09 02:04:15 PM UTC 25 50227246 ps
T257 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset_invalid.1349122751 Feb 09 02:04:13 PM UTC 25 Feb 09 02:04:15 PM UTC 25 109864595 ps
T258 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_wakeup_reset.725631751 Feb 09 02:04:14 PM UTC 25 Feb 09 02:04:17 PM UTC 25 123618009 ps
T259 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_lowpower_wakeup_race.2196402834 Feb 09 02:04:13 PM UTC 25 Feb 09 02:04:16 PM UTC 25 292991577 ps
T26 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_stress_all_with_rand_reset.3666969766 Feb 09 02:04:08 PM UTC 25 Feb 09 02:04:16 PM UTC 25 4284962016 ps
T87 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_aborted_low_power.1421599473 Feb 09 02:04:15 PM UTC 25 Feb 09 02:04:17 PM UTC 25 124540998 ps
T88 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.4174546900 Feb 09 02:04:15 PM UTC 25 Feb 09 02:04:17 PM UTC 25 37468924 ps
T89 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_stress_all_with_rand_reset.4289801733 Feb 09 02:03:53 PM UTC 25 Feb 09 02:04:17 PM UTC 25 10680097966 ps
T90 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_ctrl_config_regwen.37840218 Feb 09 02:04:15 PM UTC 25 Feb 09 02:04:17 PM UTC 25 471726878 ps
T91 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.319300767 Feb 09 02:04:15 PM UTC 25 Feb 09 02:04:17 PM UTC 25 50300549 ps
T92 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_stress_all.2172366844 Feb 09 02:04:13 PM UTC 25 Feb 09 02:04:18 PM UTC 25 860955510 ps
T93 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_global_esc.1465896777 Feb 09 02:04:16 PM UTC 25 Feb 09 02:04:18 PM UTC 25 100998812 ps
T94 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_glitch.3745099788 Feb 09 02:04:16 PM UTC 25 Feb 09 02:04:18 PM UTC 25 34320994 ps
T95 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3745637175 Feb 09 02:04:15 PM UTC 25 Feb 09 02:04:19 PM UTC 25 1080360292 ps
T260 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_lowpower_invalid.969723563 Feb 09 02:04:16 PM UTC 25 Feb 09 02:04:19 PM UTC 25 71470516 ps
T261 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1997111464 Feb 09 02:04:15 PM UTC 25 Feb 09 02:04:19 PM UTC 25 1207897818 ps
T262 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset_invalid.963527864 Feb 09 02:04:16 PM UTC 25 Feb 09 02:04:19 PM UTC 25 96720959 ps
T192 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_disable_rom_integrity_check.142912001 Feb 09 02:04:16 PM UTC 25 Feb 09 02:04:19 PM UTC 25 66226882 ps
T263 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_escalation_timeout.2719507607 Feb 09 02:04:16 PM UTC 25 Feb 09 02:04:19 PM UTC 25 167143015 ps
T264 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_smoke.2666996103 Feb 09 02:04:18 PM UTC 25 Feb 09 02:04:20 PM UTC 25 29662478 ps
T265 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup.3060037557 Feb 09 02:04:18 PM UTC 25 Feb 09 02:04:21 PM UTC 25 47438652 ps
T266 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_aborted_low_power.2308903693 Feb 09 02:04:18 PM UTC 25 Feb 09 02:04:21 PM UTC 25 172685573 ps
T267 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_lowpower_wakeup_race.1887925475 Feb 09 02:04:18 PM UTC 25 Feb 09 02:04:21 PM UTC 25 275206413 ps
T268 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup_reset.4254047362 Feb 09 02:04:18 PM UTC 25 Feb 09 02:04:21 PM UTC 25 366538461 ps
T269 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset.2702721606 Feb 09 02:04:18 PM UTC 25 Feb 09 02:04:21 PM UTC 25 84895190 ps
T270 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_esc_clk_rst_malfunc.1007274409 Feb 09 02:04:20 PM UTC 25 Feb 09 02:04:22 PM UTC 25 37941334 ps
T271 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rstmgr_intersig_mubi.3859753356 Feb 09 02:04:20 PM UTC 25 Feb 09 02:04:22 PM UTC 25 93906855 ps
T272 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_glitch.1802174749 Feb 09 02:04:20 PM UTC 25 Feb 09 02:04:22 PM UTC 25 82888296 ps
T273 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_global_esc.1888682800 Feb 09 02:04:20 PM UTC 25 Feb 09 02:04:23 PM UTC 25 24170529 ps
T49 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_stress_all_with_rand_reset.643249170 Feb 09 02:03:49 PM UTC 25 Feb 09 02:04:23 PM UTC 25 10996289647 ps
T98 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset_invalid.1372526582 Feb 09 02:04:20 PM UTC 25 Feb 09 02:04:23 PM UTC 25 155017942 ps
T99 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_disable_rom_integrity_check.2783417983 Feb 09 02:04:20 PM UTC 25 Feb 09 02:04:23 PM UTC 25 52605548 ps
T100 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_lowpower_invalid.217036869 Feb 09 02:04:21 PM UTC 25 Feb 09 02:04:23 PM UTC 25 50362965 ps
T101 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_stress_all.2578589045 Feb 09 02:04:18 PM UTC 25 Feb 09 02:04:23 PM UTC 25 1168765639 ps
T102 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_ctrl_config_regwen.3274695947 Feb 09 02:04:20 PM UTC 25 Feb 09 02:04:23 PM UTC 25 293172860 ps
T103 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_escalation_timeout.4078780533 Feb 09 02:04:20 PM UTC 25 Feb 09 02:04:23 PM UTC 25 165039612 ps
T104 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3184257990 Feb 09 02:04:18 PM UTC 25 Feb 09 02:04:24 PM UTC 25 739309986 ps
T105 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2083471909 Feb 09 02:04:20 PM UTC 25 Feb 09 02:04:25 PM UTC 25 940511497 ps
T106 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_smoke.1499743193 Feb 09 02:04:23 PM UTC 25 Feb 09 02:04:25 PM UTC 25 40512539 ps
T274 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_reset.2961211113 Feb 09 02:04:23 PM UTC 25 Feb 09 02:04:25 PM UTC 25 57903699 ps
T275 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_lowpower_wakeup_race.81219247 Feb 09 02:04:23 PM UTC 25 Feb 09 02:04:25 PM UTC 25 78645188 ps
T276 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_esc_clk_rst_malfunc.1207130785 Feb 09 02:04:25 PM UTC 25 Feb 09 02:04:27 PM UTC 25 42896196 ps
T277 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_glitch.3880096735 Feb 09 02:04:25 PM UTC 25 Feb 09 02:04:27 PM UTC 25 92706003 ps
T278 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_global_esc.2438587655 Feb 09 02:04:25 PM UTC 25 Feb 09 02:04:27 PM UTC 25 52322042 ps
T279 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_aborted_low_power.2528860918 Feb 09 02:04:25 PM UTC 25 Feb 09 02:04:28 PM UTC 25 43186200 ps
T280 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_wakeup.53891081 Feb 09 02:04:25 PM UTC 25 Feb 09 02:04:28 PM UTC 25 85319930 ps
T281 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_rstmgr_intersig_mubi.1114328801 Feb 09 02:04:25 PM UTC 25 Feb 09 02:04:28 PM UTC 25 65199743 ps
T282 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_wakeup_reset.3779959570 Feb 09 02:04:25 PM UTC 25 Feb 09 02:04:28 PM UTC 25 243968608 ps
T283 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_escalation_timeout.271598810 Feb 09 02:04:25 PM UTC 25 Feb 09 02:04:28 PM UTC 25 710551505 ps
T284 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_ctrl_config_regwen.784336481 Feb 09 02:04:25 PM UTC 25 Feb 09 02:04:29 PM UTC 25 343981415 ps
T285 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2097353980 Feb 09 02:04:25 PM UTC 25 Feb 09 02:04:29 PM UTC 25 1829096598 ps
T286 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4058498886 Feb 09 02:04:25 PM UTC 25 Feb 09 02:04:29 PM UTC 25 1035124984 ps
T287 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_disable_rom_integrity_check.3683823508 Feb 09 02:04:26 PM UTC 25 Feb 09 02:04:29 PM UTC 25 72210708 ps
T288 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_lowpower_invalid.835487215 Feb 09 02:04:27 PM UTC 25 Feb 09 02:04:29 PM UTC 25 72427114 ps
T289 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_reset_invalid.1231288854 Feb 09 02:04:26 PM UTC 25 Feb 09 02:04:30 PM UTC 25 115731252 ps
T290 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_stress_all.1274023056 Feb 09 02:04:27 PM UTC 25 Feb 09 02:04:30 PM UTC 25 862886364 ps
T291 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_stress_all.666967873 Feb 09 02:04:23 PM UTC 25 Feb 09 02:04:31 PM UTC 25 1847416227 ps
T292 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_smoke.133046457 Feb 09 02:04:35 PM UTC 25 Feb 09 02:04:37 PM UTC 25 60538579 ps
T130 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_stress_all_with_rand_reset.914221412 Feb 09 02:04:13 PM UTC 25 Feb 09 02:04:32 PM UTC 25 3677364665 ps
T293 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_smoke.1461507306 Feb 09 02:04:30 PM UTC 25 Feb 09 02:04:32 PM UTC 25 58689440 ps
T294 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_reset.2026572158 Feb 09 02:04:30 PM UTC 25 Feb 09 02:04:33 PM UTC 25 72813957 ps
T295 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_lowpower_wakeup_race.4005685992 Feb 09 02:04:30 PM UTC 25 Feb 09 02:04:33 PM UTC 25 176966111 ps
T296 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_wakeup.1676898785 Feb 09 02:04:30 PM UTC 25 Feb 09 02:04:33 PM UTC 25 236704449 ps
T297 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_wakeup_reset.2156770822 Feb 09 02:04:30 PM UTC 25 Feb 09 02:04:33 PM UTC 25 323929903 ps
T298 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_aborted_low_power.607671729 Feb 09 02:04:30 PM UTC 25 Feb 09 02:04:33 PM UTC 25 44707715 ps
T299 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_esc_clk_rst_malfunc.885499762 Feb 09 02:04:30 PM UTC 25 Feb 09 02:04:33 PM UTC 25 29292845 ps
T300 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_rstmgr_intersig_mubi.630509089 Feb 09 02:04:30 PM UTC 25 Feb 09 02:04:33 PM UTC 25 94343197 ps
T301 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_ctrl_config_regwen.4058232608 Feb 09 02:04:30 PM UTC 25 Feb 09 02:04:34 PM UTC 25 192822577 ps
T302 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.574536463 Feb 09 02:04:30 PM UTC 25 Feb 09 02:04:34 PM UTC 25 994930129 ps
T303 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_global_esc.395198658 Feb 09 02:04:32 PM UTC 25 Feb 09 02:04:34 PM UTC 25 41819478 ps
T304 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_glitch.658573613 Feb 09 02:04:32 PM UTC 25 Feb 09 02:04:34 PM UTC 25 156412927 ps
T193 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_disable_rom_integrity_check.1423459054 Feb 09 02:04:32 PM UTC 25 Feb 09 02:04:34 PM UTC 25 93677239 ps
T305 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_escalation_timeout.589858643 Feb 09 02:04:32 PM UTC 25 Feb 09 02:04:35 PM UTC 25 158453178 ps
T306 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_reset_invalid.180011113 Feb 09 02:04:32 PM UTC 25 Feb 09 02:04:35 PM UTC 25 143979373 ps
T131 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_stress_all_with_rand_reset.4209461522 Feb 09 02:04:16 PM UTC 25 Feb 09 02:04:36 PM UTC 25 8522968078 ps
T307 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.891826092 Feb 09 02:04:30 PM UTC 25 Feb 09 02:04:36 PM UTC 25 925232072 ps
T308 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_lowpower_invalid.2817467449 Feb 09 02:04:35 PM UTC 25 Feb 09 02:04:37 PM UTC 25 56215292 ps
T309 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_reset.2960788541 Feb 09 02:04:35 PM UTC 25 Feb 09 02:04:38 PM UTC 25 124283574 ps
T310 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_esc_clk_rst_malfunc.4156770434 Feb 09 02:04:35 PM UTC 25 Feb 09 02:04:38 PM UTC 25 34146884 ps
T311 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_lowpower_wakeup_race.3100601517 Feb 09 02:04:35 PM UTC 25 Feb 09 02:04:38 PM UTC 25 48640866 ps
T312 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_rstmgr_intersig_mubi.2849856346 Feb 09 02:04:35 PM UTC 25 Feb 09 02:04:38 PM UTC 25 100457967 ps
T313 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_wakeup.916245121 Feb 09 02:04:35 PM UTC 25 Feb 09 02:04:38 PM UTC 25 255380072 ps
T314 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_aborted_low_power.2246672861 Feb 09 02:04:35 PM UTC 25 Feb 09 02:04:38 PM UTC 25 33053645 ps
T315 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_wakeup_reset.3269399942 Feb 09 02:04:35 PM UTC 25 Feb 09 02:04:38 PM UTC 25 403727218 ps
T316 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_ctrl_config_regwen.1762283329 Feb 09 02:04:35 PM UTC 25 Feb 09 02:04:39 PM UTC 25 245056495 ps
T46 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_stress_all_with_rand_reset.198013003 Feb 09 02:04:02 PM UTC 25 Feb 09 02:04:39 PM UTC 25 9433074290 ps
T317 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_glitch.485645718 Feb 09 02:04:37 PM UTC 25 Feb 09 02:04:39 PM UTC 25 86240537 ps
T50 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_stress_all_with_rand_reset.3676407940 Feb 09 02:04:27 PM UTC 25 Feb 09 02:04:39 PM UTC 25 20099533332 ps
T318 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_global_esc.2328404246 Feb 09 02:04:37 PM UTC 25 Feb 09 02:04:39 PM UTC 25 33914476 ps
T319 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1072461893 Feb 09 02:04:35 PM UTC 25 Feb 09 02:04:39 PM UTC 25 1097934487 ps
T320 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_disable_rom_integrity_check.1070299593 Feb 09 02:04:37 PM UTC 25 Feb 09 02:04:40 PM UTC 25 58432786 ps
T321 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2159777249 Feb 09 02:04:35 PM UTC 25 Feb 09 02:04:40 PM UTC 25 1017066973 ps
T322 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_escalation_timeout.1035798008 Feb 09 02:04:37 PM UTC 25 Feb 09 02:04:40 PM UTC 25 166554155 ps
T323 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_stress_all.2930332552 Feb 09 02:04:35 PM UTC 25 Feb 09 02:04:41 PM UTC 25 1917605601 ps
T324 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_lowpower_invalid.4177040381 Feb 09 02:04:39 PM UTC 25 Feb 09 02:04:41 PM UTC 25 40237154 ps
T325 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_lowpower_wakeup_race.2486059227 Feb 09 02:04:39 PM UTC 25 Feb 09 02:04:41 PM UTC 25 76186873 ps
T326 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_smoke.177118625 Feb 09 02:04:39 PM UTC 25 Feb 09 02:04:41 PM UTC 25 31257361 ps
T327 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_wakeup_reset.1877231419 Feb 09 02:04:39 PM UTC 25 Feb 09 02:04:41 PM UTC 25 150640211 ps
T328 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_reset_invalid.737808002 Feb 09 02:04:39 PM UTC 25 Feb 09 02:04:41 PM UTC 25 179354911 ps