93b7cb99d8| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rstmgr_smoke | 0 | 50 | 0.00 | ||
| V1 | csr_hw_reset | rstmgr_csr_hw_reset | 0 | 5 | 0.00 | ||
| V1 | csr_rw | rstmgr_csr_rw | 0 | 20 | 0.00 | ||
| V1 | csr_bit_bash | rstmgr_csr_bit_bash | 0 | 5 | 0.00 | ||
| V1 | csr_aliasing | rstmgr_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | rstmgr_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | rstmgr_csr_rw | 0 | 20 | 0.00 | ||
| rstmgr_csr_aliasing | 0 | 5 | 0.00 | ||||
| V1 | TOTAL | 0 | 105 | 0.00 | |||
| V2 | reset_stretcher | rstmgr_por_stretcher | 0 | 50 | 0.00 | ||
| V2 | sw_rst | rstmgr_sw_rst | 0 | 50 | 0.00 | ||
| V2 | sw_rst_reset_race | rstmgr_sw_rst_reset_race | 0 | 50 | 0.00 | ||
| V2 | reset_info | rstmgr_reset | 0 | 50 | 0.00 | ||
| V2 | cpu_info | rstmgr_reset | 0 | 50 | 0.00 | ||
| V2 | alert_info | rstmgr_reset | 0 | 50 | 0.00 | ||
| V2 | reset_info_capture | rstmgr_reset | 0 | 50 | 0.00 | ||
| V2 | stress_all | rstmgr_stress_all | 0 | 50 | 0.00 | ||
| V2 | alert_test | rstmgr_alert_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | rstmgr_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_illegal_access | rstmgr_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_outstanding_access | rstmgr_csr_hw_reset | 0 | 5 | 0.00 | ||
| rstmgr_csr_rw | 0 | 20 | 0.00 | ||||
| rstmgr_csr_aliasing | 0 | 5 | 0.00 | ||||
| rstmgr_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | tl_d_partial_access | rstmgr_csr_hw_reset | 0 | 5 | 0.00 | ||
| rstmgr_csr_rw | 0 | 20 | 0.00 | ||||
| rstmgr_csr_aliasing | 0 | 5 | 0.00 | ||||
| rstmgr_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | TOTAL | 0 | 340 | 0.00 | |||
| V2S | tl_intg_err | rstmgr_sec_cm | 0 | 5 | 0.00 | ||
| rstmgr_tl_intg_err | 0 | 20 | 0.00 | ||||
| V2S | prim_count_check | rstmgr_sec_cm | 0 | 5 | 0.00 | ||
| V2S | prim_fsm_check | rstmgr_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_bus_integrity | rstmgr_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | sec_cm_scan_intersig_mubi | rstmgr_sec_cm_scan_intersig_mubi | 0 | 50 | 0.00 | ||
| V2S | sec_cm_leaf_rst_bkgn_chk | rstmgr_leaf_rst_cnsty | 0 | 50 | 0.00 | ||
| V2S | sec_cm_leaf_rst_shadow | rstmgr_leaf_rst_shadow_attack | 0 | 50 | 0.00 | ||
| V2S | sec_cm_leaf_fsm_sparse | rstmgr_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_sw_rst_config_regwen | rstmgr_csr_rw | 0 | 20 | 0.00 | ||
| V2S | sec_cm_dump_ctrl_config_regwen | rstmgr_csr_rw | 0 | 20 | 0.00 | ||
| V2S | TOTAL | 0 | 175 | 0.00 | |||
| V3 | stress_all_with_rand_reset | rstmgr_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 0 | 620 | 0.00 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 0 | 0.00 |
| V2 | 8 | 8 | 0 | 0.00 |
| V2S | 5 | 5 | 0 | 0.00 |
| V3 | 1 | 0 | 0 | 0.00 |
Job killed most likely because its dependent job failed. has 622 failures:
0.rstmgr_smoke.32466602193341258106738247348437018623619996031655615211329301541914698492284
Log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/0.rstmgr_smoke/latest/run.log
1.rstmgr_smoke.92801776287135922931684575067912856778070413822336104626726406136681780627060
Log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/1.rstmgr_smoke/latest/run.log
... and 48 more failures.
0.rstmgr_por_stretcher.110117293951560557295136805321682229241560529766016569357364695478279870017537
Log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/0.rstmgr_por_stretcher/latest/run.log
1.rstmgr_por_stretcher.19163089441367964986998568841886061308412590777126592591848390737127811193859
Log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/1.rstmgr_por_stretcher/latest/run.log
... and 48 more failures.
0.rstmgr_reset.51008546621095630216303577699639296858948838865585729332087644063725556489186
Log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/0.rstmgr_reset/latest/run.log
1.rstmgr_reset.10381188364439553625848656753227809162960223868902647926630770117161709284990
Log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/1.rstmgr_reset/latest/run.log
... and 48 more failures.
0.rstmgr_sw_rst_reset_race.91157548994659049993457728097689644027674302390860534694658350700323029124208
Log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/0.rstmgr_sw_rst_reset_race/latest/run.log
1.rstmgr_sw_rst_reset_race.23187830676109514420740357763787852280554040039696049576457056904448515842548
Log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/1.rstmgr_sw_rst_reset_race/latest/run.log
... and 48 more failures.
0.rstmgr_sw_rst.47705589410415310622151338305329813270104160280000090367810754184072690123451
Log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/0.rstmgr_sw_rst/latest/run.log
1.rstmgr_sw_rst.28550799405321202601245433304568867064471872960779846420771882940376002835344
Log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/1.rstmgr_sw_rst/latest/run.log
... and 48 more failures.
Job rstmgr-sim-vcs_build_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
default
Log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/default/build.log
Job ID: smart:d00c5be8-02fb-457d-9d4c-714ea3b83929
Job rstmgr-sim-vcs_build_cover_reg_top killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
cover_reg_top
Log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/build.log
Job ID: smart:2cede12c-042d-4070-b13e-a4ccc6ae0556