RSTMGR Simulation Results

Sunday February 18 2024 20:02:30 UTC

GitHub Revision: 8faf04697a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 18983509472502570446328716692660256492766541929441074968843370054317032656232

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rstmgr_smoke	1.590s	265.788us	50	50	100.00
V1	csr_hw_reset	rstmgr_csr_hw_reset	0.920s	142.739us	5	5	100.00
V1	csr_rw	rstmgr_csr_rw	0.880s	87.147us	20	20	100.00
V1	csr_bit_bash	rstmgr_csr_bit_bash	6.010s	489.702us	5	5	100.00
V1	csr_aliasing	rstmgr_csr_aliasing	2.570s	459.525us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rstmgr_csr_mem_rw_with_rand_reset	4.080s	632.698us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rstmgr_csr_rw	0.880s	87.147us	20	20	100.00
		rstmgr_csr_aliasing	2.570s	459.525us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	reset_stretcher	rstmgr_por_stretcher	0.990s	258.078us	50	50	100.00
V2	sw_rst	rstmgr_sw_rst	2.870s	474.695us	50	50	100.00
V2	sw_rst_reset_race	rstmgr_sw_rst_reset_race	1.510s	276.117us	50	50	100.00
V2	reset_info	rstmgr_reset	7.540s	1.772ms	50	50	100.00
V2	cpu_info	rstmgr_reset	7.540s	1.772ms	50	50	100.00
V2	alert_info	rstmgr_reset	7.540s	1.772ms	50	50	100.00
V2	reset_info_capture	rstmgr_reset	7.540s	1.772ms	50	50	100.00
V2	stress_all	rstmgr_stress_all	52.740s	14.699ms	50	50	100.00
V2	alert_test	rstmgr_alert_test	0.930s	76.410us	50	50	100.00
V2	tl_d_oob_addr_access	rstmgr_tl_errors	4.110s	576.166us	20	20	100.00
V2	tl_d_illegal_access	rstmgr_tl_errors	4.110s	576.166us	20	20	100.00
V2	tl_d_outstanding_access	rstmgr_csr_hw_reset	0.920s	142.739us	5	5	100.00
		rstmgr_csr_rw	0.880s	87.147us	20	20	100.00
		rstmgr_csr_aliasing	2.570s	459.525us	5	5	100.00
		rstmgr_same_csr_outstanding	1.760s	270.237us	20	20	100.00
V2	tl_d_partial_access	rstmgr_csr_hw_reset	0.920s	142.739us	5	5	100.00
		rstmgr_csr_rw	0.880s	87.147us	20	20	100.00
		rstmgr_csr_aliasing	2.570s	459.525us	5	5	100.00
		rstmgr_same_csr_outstanding	1.760s	270.237us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	rstmgr_sec_cm	43.440s	26.461ms	5	5	100.00
		rstmgr_tl_intg_err	3.310s	915.744us	20	20	100.00
V2S	prim_count_check	rstmgr_sec_cm	43.440s	26.461ms	5	5	100.00
V2S	prim_fsm_check	rstmgr_sec_cm	43.440s	26.461ms	5	5	100.00
V2S	sec_cm_bus_integrity	rstmgr_tl_intg_err	3.310s	915.744us	20	20	100.00
V2S	sec_cm_scan_intersig_mubi	rstmgr_sec_cm_scan_intersig_mubi	1.360s	151.123us	50	50	100.00
V2S	sec_cm_leaf_rst_bkgn_chk	rstmgr_leaf_rst_cnsty	10.100s	2.356ms	50	50	100.00
V2S	sec_cm_leaf_rst_shadow	rstmgr_leaf_rst_shadow_attack	1.230s	243.707us	50	50	100.00
V2S	sec_cm_leaf_fsm_sparse	rstmgr_sec_cm	43.440s	26.461ms	5	5	100.00
V2S	sec_cm_sw_rst_config_regwen	rstmgr_csr_rw	0.880s	87.147us	20	20	100.00
V2S	sec_cm_dump_ctrl_config_regwen	rstmgr_csr_rw	0.880s	87.147us	20	20	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	rstmgr_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			620	620	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	5	5	5	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.44	99.40	99.31	99.88	--	99.83	99.46	98.77

Past Results

• Latest
• rstmgr_cnsty_chk
• 2024.02.14_22.13.09
• 2024.02.08_09.29.02
• 2024.02.05_04.52.36
• 2024.01.31_21.06.58