RSTMGR Simulation Results

Tuesday March 19 2024 19:02:40 UTC

GitHub Revision: f7fc348358

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 93166527750821992054916907919379261408154533955814283538537589225972237641118

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rstmgr_smoke 1.680s 254.417us 50 50 100.00
V1 csr_hw_reset rstmgr_csr_hw_reset 0.990s 115.283us 5 5 100.00
V1 csr_rw rstmgr_csr_rw 0.930s 84.114us 20 20 100.00
V1 csr_bit_bash rstmgr_csr_bit_bash 8.630s 1.559ms 5 5 100.00
V1 csr_aliasing rstmgr_csr_aliasing 2.890s 442.994us 5 5 100.00
V1 csr_mem_rw_with_rand_reset rstmgr_csr_mem_rw_with_rand_reset 1.830s 177.959us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rstmgr_csr_rw 0.930s 84.114us 20 20 100.00
rstmgr_csr_aliasing 2.890s 442.994us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 reset_stretcher rstmgr_por_stretcher 1.070s 209.406us 50 50 100.00
V2 sw_rst rstmgr_sw_rst 3.190s 554.914us 50 50 100.00
V2 sw_rst_reset_race rstmgr_sw_rst_reset_race 1.740s 299.571us 50 50 100.00
V2 reset_info rstmgr_reset 8.060s 2.229ms 50 50 100.00
V2 cpu_info rstmgr_reset 8.060s 2.229ms 50 50 100.00
V2 alert_info rstmgr_reset 8.060s 2.229ms 50 50 100.00
V2 reset_info_capture rstmgr_reset 8.060s 2.229ms 50 50 100.00
V2 stress_all rstmgr_stress_all 43.490s 12.856ms 50 50 100.00
V2 alert_test rstmgr_alert_test 1.060s 197.957us 50 50 100.00
V2 tl_d_oob_addr_access rstmgr_tl_errors 3.600s 489.793us 20 20 100.00
V2 tl_d_illegal_access rstmgr_tl_errors 3.600s 489.793us 20 20 100.00
V2 tl_d_outstanding_access rstmgr_csr_hw_reset 0.990s 115.283us 5 5 100.00
rstmgr_csr_rw 0.930s 84.114us 20 20 100.00
rstmgr_csr_aliasing 2.890s 442.994us 5 5 100.00
rstmgr_same_csr_outstanding 1.560s 237.690us 20 20 100.00
V2 tl_d_partial_access rstmgr_csr_hw_reset 0.990s 115.283us 5 5 100.00
rstmgr_csr_rw 0.930s 84.114us 20 20 100.00
rstmgr_csr_aliasing 2.890s 442.994us 5 5 100.00
rstmgr_same_csr_outstanding 1.560s 237.690us 20 20 100.00
V2 TOTAL 340 340 100.00
V2S tl_intg_err rstmgr_sec_cm 29.160s 16.524ms 5 5 100.00
rstmgr_tl_intg_err 3.240s 792.505us 20 20 100.00
V2S prim_count_check rstmgr_sec_cm 29.160s 16.524ms 5 5 100.00
V2S prim_fsm_check rstmgr_sec_cm 29.160s 16.524ms 5 5 100.00
V2S sec_cm_bus_integrity rstmgr_tl_intg_err 3.240s 792.505us 20 20 100.00
V2S sec_cm_scan_intersig_mubi rstmgr_sec_cm_scan_intersig_mubi 1.350s 178.790us 50 50 100.00
V2S sec_cm_leaf_rst_bkgn_chk rstmgr_leaf_rst_cnsty 9.570s 2.368ms 50 50 100.00
V2S sec_cm_leaf_rst_shadow rstmgr_leaf_rst_shadow_attack 1.250s 244.376us 50 50 100.00
V2S sec_cm_leaf_fsm_sparse rstmgr_sec_cm 29.160s 16.524ms 5 5 100.00
V2S sec_cm_sw_rst_config_regwen rstmgr_csr_rw 0.930s 84.114us 20 20 100.00
V2S sec_cm_dump_ctrl_config_regwen rstmgr_csr_rw 0.930s 84.114us 20 20 100.00
V2S TOTAL 175 175 100.00
V3 stress_all_with_rand_reset rstmgr_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 620 620 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 8 8 8 100.00
V2S 5 5 5 100.00
V3 1 0 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.43 99.40 99.24 99.88 -- 99.83 99.46 98.77

Past Results