RSTMGR Simulation Results

Sunday May 05 2024 19:05:13 UTC

GitHub Revision: d0c52cdadd

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 81579111587980121648949789282063322266496016209500883225240730864920651071561

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rstmgr_smoke 1.760s 255.984us 50 50 100.00
V1 csr_hw_reset rstmgr_csr_hw_reset 1.010s 152.734us 5 5 100.00
V1 csr_rw rstmgr_csr_rw 0.880s 81.161us 20 20 100.00
V1 csr_bit_bash rstmgr_csr_bit_bash 10.620s 2.301ms 5 5 100.00
V1 csr_aliasing rstmgr_csr_aliasing 2.560s 359.240us 5 5 100.00
V1 csr_mem_rw_with_rand_reset rstmgr_csr_mem_rw_with_rand_reset 1.980s 188.416us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rstmgr_csr_rw 0.880s 81.161us 20 20 100.00
rstmgr_csr_aliasing 2.560s 359.240us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 reset_stretcher rstmgr_por_stretcher 1.010s 242.614us 50 50 100.00
V2 sw_rst rstmgr_sw_rst 2.810s 537.541us 50 50 100.00
V2 sw_rst_reset_race rstmgr_sw_rst_reset_race 1.690s 282.499us 50 50 100.00
V2 reset_info rstmgr_reset 8.310s 2.306ms 50 50 100.00
V2 cpu_info rstmgr_reset 8.310s 2.306ms 50 50 100.00
V2 alert_info rstmgr_reset 8.310s 2.306ms 50 50 100.00
V2 reset_info_capture rstmgr_reset 8.310s 2.306ms 50 50 100.00
V2 stress_all rstmgr_stress_all 1.205m 19.645ms 50 50 100.00
V2 alert_test rstmgr_alert_test 0.910s 93.108us 50 50 100.00
V2 tl_d_oob_addr_access rstmgr_tl_errors 3.870s 606.962us 20 20 100.00
V2 tl_d_illegal_access rstmgr_tl_errors 3.870s 606.962us 20 20 100.00
V2 tl_d_outstanding_access rstmgr_csr_hw_reset 1.010s 152.734us 5 5 100.00
rstmgr_csr_rw 0.880s 81.161us 20 20 100.00
rstmgr_csr_aliasing 2.560s 359.240us 5 5 100.00
rstmgr_same_csr_outstanding 1.740s 232.541us 20 20 100.00
V2 tl_d_partial_access rstmgr_csr_hw_reset 1.010s 152.734us 5 5 100.00
rstmgr_csr_rw 0.880s 81.161us 20 20 100.00
rstmgr_csr_aliasing 2.560s 359.240us 5 5 100.00
rstmgr_same_csr_outstanding 1.740s 232.541us 20 20 100.00
V2 TOTAL 340 340 100.00
V2S tl_intg_err rstmgr_sec_cm 26.710s 16.509ms 5 5 100.00
rstmgr_tl_intg_err 3.570s 926.961us 20 20 100.00
V2S prim_count_check rstmgr_sec_cm 26.710s 16.509ms 5 5 100.00
V2S prim_fsm_check rstmgr_sec_cm 26.710s 16.509ms 5 5 100.00
V2S sec_cm_bus_integrity rstmgr_tl_intg_err 3.570s 926.961us 20 20 100.00
V2S sec_cm_scan_intersig_mubi rstmgr_sec_cm_scan_intersig_mubi 1.300s 180.786us 50 50 100.00
V2S sec_cm_leaf_rst_bkgn_chk rstmgr_leaf_rst_cnsty 8.930s 2.359ms 50 50 100.00
V2S sec_cm_leaf_rst_shadow rstmgr_leaf_rst_shadow_attack 1.210s 243.702us 50 50 100.00
V2S sec_cm_leaf_fsm_sparse rstmgr_sec_cm 26.710s 16.509ms 5 5 100.00
V2S sec_cm_sw_rst_config_regwen rstmgr_csr_rw 0.880s 81.161us 20 20 100.00
V2S sec_cm_dump_ctrl_config_regwen rstmgr_csr_rw 0.880s 81.161us 20 20 100.00
V2S TOTAL 175 175 100.00
V3 stress_all_with_rand_reset rstmgr_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 620 620 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 8 8 8 100.00
V2S 5 5 5 100.00
V3 1 0 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.43 99.40 99.24 99.87 -- 99.83 99.46 98.77

Past Results