RSTMGR Simulation Results

Tuesday June 04 2024 19:02:20 UTC

GitHub Revision: a182fcef27

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 115716131103921631007013649731972014580281041353363476420230431751664670300928

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rstmgr_smoke	1.720s	253.913us	50	50	100.00
V1	csr_hw_reset	rstmgr_csr_hw_reset	0.940s	154.484us	5	5	100.00
V1	csr_rw	rstmgr_csr_rw	0.890s	89.201us	20	20	100.00
V1	csr_bit_bash	rstmgr_csr_bit_bash	7.810s	1.560ms	5	5	100.00
V1	csr_aliasing	rstmgr_csr_aliasing	1.800s	269.566us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rstmgr_csr_mem_rw_with_rand_reset	1.970s	200.454us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rstmgr_csr_rw	0.890s	89.201us	20	20	100.00
		rstmgr_csr_aliasing	1.800s	269.566us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	reset_stretcher	rstmgr_por_stretcher	1.070s	219.118us	50	50	100.00
V2	sw_rst	rstmgr_sw_rst	2.930s	520.786us	50	50	100.00
V2	sw_rst_reset_race	rstmgr_sw_rst_reset_race	1.590s	270.155us	50	50	100.00
V2	reset_info	rstmgr_reset	8.090s	1.973ms	50	50	100.00
V2	cpu_info	rstmgr_reset	8.090s	1.973ms	50	50	100.00
V2	alert_info	rstmgr_reset	8.090s	1.973ms	50	50	100.00
V2	reset_info_capture	rstmgr_reset	8.090s	1.973ms	50	50	100.00
V2	stress_all	rstmgr_stress_all	1.123m	18.002ms	50	50	100.00
V2	alert_test	rstmgr_alert_test	0.890s	82.611us	50	50	100.00
V2	tl_d_oob_addr_access	rstmgr_tl_errors	4.060s	619.786us	20	20	100.00
V2	tl_d_illegal_access	rstmgr_tl_errors	4.060s	619.786us	20	20	100.00
V2	tl_d_outstanding_access	rstmgr_csr_hw_reset	0.940s	154.484us	5	5	100.00
		rstmgr_csr_rw	0.890s	89.201us	20	20	100.00
		rstmgr_csr_aliasing	1.800s	269.566us	5	5	100.00
		rstmgr_same_csr_outstanding	1.650s	284.611us	20	20	100.00
V2	tl_d_partial_access	rstmgr_csr_hw_reset	0.940s	154.484us	5	5	100.00
		rstmgr_csr_rw	0.890s	89.201us	20	20	100.00
		rstmgr_csr_aliasing	1.800s	269.566us	5	5	100.00
		rstmgr_same_csr_outstanding	1.650s	284.611us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	rstmgr_sec_cm	31.540s	16.517ms	5	5	100.00
		rstmgr_tl_intg_err	3.250s	958.871us	20	20	100.00
V2S	prim_count_check	rstmgr_sec_cm	31.540s	16.517ms	5	5	100.00
V2S	prim_fsm_check	rstmgr_sec_cm	31.540s	16.517ms	5	5	100.00
V2S	sec_cm_bus_integrity	rstmgr_tl_intg_err	3.250s	958.871us	20	20	100.00
V2S	sec_cm_scan_intersig_mubi	rstmgr_sec_cm_scan_intersig_mubi	1.310s	187.242us	50	50	100.00
V2S	sec_cm_leaf_rst_bkgn_chk	rstmgr_leaf_rst_cnsty	9.270s	2.355ms	50	50	100.00
V2S	sec_cm_leaf_rst_shadow	rstmgr_leaf_rst_shadow_attack	1.220s	244.580us	50	50	100.00
V2S	sec_cm_leaf_fsm_sparse	rstmgr_sec_cm	31.540s	16.517ms	5	5	100.00
V2S	sec_cm_sw_rst_config_regwen	rstmgr_csr_rw	0.890s	89.201us	20	20	100.00
V2S	sec_cm_dump_ctrl_config_regwen	rstmgr_csr_rw	0.890s	89.201us	20	20	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	rstmgr_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			620	620	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	5	5	5	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.44	99.40	99.31	99.87	--	99.83	99.46	98.77

Past Results

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• lint
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• 2024.05.29_03.45.33
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