RSTMGR Simulation Results

Monday June 10 2024 23:28:43 UTC

GitHub Revision: a8c9c17a8c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 72227341233107832543509484606850665418885932500709631655793413524197290927900

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rstmgr_smoke	1.650s	248.573us	50	50	100.00
V1	csr_hw_reset	rstmgr_csr_hw_reset	1.070s	119.781us	5	5	100.00
V1	csr_rw	rstmgr_csr_rw	0.910s	87.659us	20	20	100.00
V1	csr_bit_bash	rstmgr_csr_bit_bash	10.000s	2.283ms	5	5	100.00
V1	csr_aliasing	rstmgr_csr_aliasing	2.600s	400.041us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rstmgr_csr_mem_rw_with_rand_reset	1.720s	170.151us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rstmgr_csr_rw	0.910s	87.659us	20	20	100.00
		rstmgr_csr_aliasing	2.600s	400.041us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	reset_stretcher	rstmgr_por_stretcher	1.120s	232.124us	50	50	100.00
V2	sw_rst	rstmgr_sw_rst	2.720s	447.618us	50	50	100.00
V2	sw_rst_reset_race	rstmgr_sw_rst_reset_race	1.570s	266.167us	50	50	100.00
V2	reset_info	rstmgr_reset	7.260s	2.016ms	50	50	100.00
V2	cpu_info	rstmgr_reset	7.260s	2.016ms	50	50	100.00
V2	alert_info	rstmgr_reset	7.260s	2.016ms	50	50	100.00
V2	reset_info_capture	rstmgr_reset	7.260s	2.016ms	50	50	100.00
V2	stress_all	rstmgr_stress_all	59.640s	16.168ms	50	50	100.00
V2	alert_test	rstmgr_alert_test	0.890s	82.737us	50	50	100.00
V2	tl_d_oob_addr_access	rstmgr_tl_errors	3.690s	425.914us	20	20	100.00
V2	tl_d_illegal_access	rstmgr_tl_errors	3.690s	425.914us	20	20	100.00
V2	tl_d_outstanding_access	rstmgr_csr_hw_reset	1.070s	119.781us	5	5	100.00
		rstmgr_csr_rw	0.910s	87.659us	20	20	100.00
		rstmgr_csr_aliasing	2.600s	400.041us	5	5	100.00
		rstmgr_same_csr_outstanding	1.600s	263.358us	20	20	100.00
V2	tl_d_partial_access	rstmgr_csr_hw_reset	1.070s	119.781us	5	5	100.00
		rstmgr_csr_rw	0.910s	87.659us	20	20	100.00
		rstmgr_csr_aliasing	2.600s	400.041us	5	5	100.00
		rstmgr_same_csr_outstanding	1.600s	263.358us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	rstmgr_sec_cm	26.390s	17.682ms	5	5	100.00
		rstmgr_tl_intg_err	3.480s	928.542us	20	20	100.00
V2S	prim_count_check	rstmgr_sec_cm	26.390s	17.682ms	5	5	100.00
V2S	prim_fsm_check	rstmgr_sec_cm	26.390s	17.682ms	5	5	100.00
V2S	sec_cm_bus_integrity	rstmgr_tl_intg_err	3.480s	928.542us	20	20	100.00
V2S	sec_cm_scan_intersig_mubi	rstmgr_sec_cm_scan_intersig_mubi	1.300s	176.982us	50	50	100.00
V2S	sec_cm_leaf_rst_bkgn_chk	rstmgr_leaf_rst_cnsty	9.130s	2.351ms	49	50	98.00
V2S	sec_cm_leaf_rst_shadow	rstmgr_leaf_rst_shadow_attack	1.220s	244.654us	50	50	100.00
V2S	sec_cm_leaf_fsm_sparse	rstmgr_sec_cm	26.390s	17.682ms	5	5	100.00
V2S	sec_cm_sw_rst_config_regwen	rstmgr_csr_rw	0.910s	87.659us	20	20	100.00
V2S	sec_cm_dump_ctrl_config_regwen	rstmgr_csr_rw	0.910s	87.659us	20	20	100.00
V2S		TOTAL			174	175	99.43
V3	stress_all_with_rand_reset	rstmgr_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			619	620	99.84

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	5	5	4	80.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.44	99.40	99.31	99.87	--	99.83	99.46	98.77

Failure Buckets

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_cnsty_fault did not trigger max_delay:* has 1 failures:
  • Test rstmgr_leaf_rst_cnsty has 1 failures.

    • 42.rstmgr_leaf_rst_cnsty.98514040132579703654579465888924705188040225393116984778538052755207914036656
      Line 281, in log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/42.rstmgr_leaf_rst_cnsty/latest/run.log

        UVM_ERROR @ 230633466 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_cnsty_fault did not trigger max_delay:20
        UVM_INFO @ 230633466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• rstmgr_cnsty_chk
• lint
• 2024.06.10_07.10.33
• 2024.06.08_13.31.33
• 2024.06.07_05.15.20
• 2024.06.06_11.25.16
• 2024.06.05_04.22.42