RSTMGR Simulation Results

Wednesday June 05 2024 22:14:46 UTC

GitHub Revision: b29ffbb03c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 104714960319679935410420483500971829136303708457300037460974663680452494898918

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rstmgr_smoke 1.690s 264.565us 50 50 100.00
V1 csr_hw_reset rstmgr_csr_hw_reset 0.970s 138.277us 5 5 100.00
V1 csr_rw rstmgr_csr_rw 0.920s 81.907us 20 20 100.00
V1 csr_bit_bash rstmgr_csr_bit_bash 8.930s 1.986ms 5 5 100.00
V1 csr_aliasing rstmgr_csr_aliasing 2.580s 420.412us 5 5 100.00
V1 csr_mem_rw_with_rand_reset rstmgr_csr_mem_rw_with_rand_reset 2.060s 204.532us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rstmgr_csr_rw 0.920s 81.907us 20 20 100.00
rstmgr_csr_aliasing 2.580s 420.412us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 reset_stretcher rstmgr_por_stretcher 1.010s 158.902us 50 50 100.00
V2 sw_rst rstmgr_sw_rst 3.140s 539.737us 50 50 100.00
V2 sw_rst_reset_race rstmgr_sw_rst_reset_race 1.540s 287.737us 50 50 100.00
V2 reset_info rstmgr_reset 8.200s 1.943ms 50 50 100.00
V2 cpu_info rstmgr_reset 8.200s 1.943ms 50 50 100.00
V2 alert_info rstmgr_reset 8.200s 1.943ms 50 50 100.00
V2 reset_info_capture rstmgr_reset 8.200s 1.943ms 50 50 100.00
V2 stress_all rstmgr_stress_all 48.120s 14.403ms 50 50 100.00
V2 alert_test rstmgr_alert_test 0.880s 99.028us 50 50 100.00
V2 tl_d_oob_addr_access rstmgr_tl_errors 4.580s 626.110us 20 20 100.00
V2 tl_d_illegal_access rstmgr_tl_errors 4.580s 626.110us 20 20 100.00
V2 tl_d_outstanding_access rstmgr_csr_hw_reset 0.970s 138.277us 5 5 100.00
rstmgr_csr_rw 0.920s 81.907us 20 20 100.00
rstmgr_csr_aliasing 2.580s 420.412us 5 5 100.00
rstmgr_same_csr_outstanding 1.580s 257.285us 20 20 100.00
V2 tl_d_partial_access rstmgr_csr_hw_reset 0.970s 138.277us 5 5 100.00
rstmgr_csr_rw 0.920s 81.907us 20 20 100.00
rstmgr_csr_aliasing 2.580s 420.412us 5 5 100.00
rstmgr_same_csr_outstanding 1.580s 257.285us 20 20 100.00
V2 TOTAL 340 340 100.00
V2S tl_intg_err rstmgr_sec_cm 28.060s 16.516ms 5 5 100.00
rstmgr_tl_intg_err 3.700s 889.571us 20 20 100.00
V2S prim_count_check rstmgr_sec_cm 28.060s 16.516ms 5 5 100.00
V2S prim_fsm_check rstmgr_sec_cm 28.060s 16.516ms 5 5 100.00
V2S sec_cm_bus_integrity rstmgr_tl_intg_err 3.700s 889.571us 20 20 100.00
V2S sec_cm_scan_intersig_mubi rstmgr_sec_cm_scan_intersig_mubi 1.350s 170.163us 50 50 100.00
V2S sec_cm_leaf_rst_bkgn_chk rstmgr_leaf_rst_cnsty 9.060s 2.364ms 50 50 100.00
V2S sec_cm_leaf_rst_shadow rstmgr_leaf_rst_shadow_attack 1.160s 243.699us 50 50 100.00
V2S sec_cm_leaf_fsm_sparse rstmgr_sec_cm 28.060s 16.516ms 5 5 100.00
V2S sec_cm_sw_rst_config_regwen rstmgr_csr_rw 0.920s 81.907us 20 20 100.00
V2S sec_cm_dump_ctrl_config_regwen rstmgr_csr_rw 0.920s 81.907us 20 20 100.00
V2S TOTAL 175 175 100.00
V3 stress_all_with_rand_reset rstmgr_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 620 620 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 8 8 8 100.00
V2S 5 5 5 100.00
V3 1 0 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.44 99.40 99.31 99.87 -- 99.83 99.46 98.77

Past Results