RSTMGR Simulation Results

Tuesday June 11 2024 19:02:38 UTC

GitHub Revision: dd5ad5fb77

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 66418170746903624595625818392428707033482455256751560525176982524210226376736

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rstmgr_smoke	1.680s	236.982us	50	50	100.00
V1	csr_hw_reset	rstmgr_csr_hw_reset	0.900s	99.780us	5	5	100.00
V1	csr_rw	rstmgr_csr_rw	0.870s	63.369us	20	20	100.00
V1	csr_bit_bash	rstmgr_csr_bit_bash	10.520s	2.283ms	5	5	100.00
V1	csr_aliasing	rstmgr_csr_aliasing	2.610s	433.332us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rstmgr_csr_mem_rw_with_rand_reset	1.840s	195.706us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rstmgr_csr_rw	0.870s	63.369us	20	20	100.00
		rstmgr_csr_aliasing	2.610s	433.332us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	reset_stretcher	rstmgr_por_stretcher	1.010s	217.749us	50	50	100.00
V2	sw_rst	rstmgr_sw_rst	2.890s	560.252us	50	50	100.00
V2	sw_rst_reset_race	rstmgr_sw_rst_reset_race	1.510s	257.367us	50	50	100.00
V2	reset_info	rstmgr_reset	7.740s	2.131ms	50	50	100.00
V2	cpu_info	rstmgr_reset	7.740s	2.131ms	50	50	100.00
V2	alert_info	rstmgr_reset	7.740s	2.131ms	50	50	100.00
V2	reset_info_capture	rstmgr_reset	7.740s	2.131ms	50	50	100.00
V2	stress_all	rstmgr_stress_all	48.990s	15.544ms	50	50	100.00
V2	alert_test	rstmgr_alert_test	0.890s	152.246us	50	50	100.00
V2	tl_d_oob_addr_access	rstmgr_tl_errors	3.380s	488.863us	20	20	100.00
V2	tl_d_illegal_access	rstmgr_tl_errors	3.380s	488.863us	20	20	100.00
V2	tl_d_outstanding_access	rstmgr_csr_hw_reset	0.900s	99.780us	5	5	100.00
		rstmgr_csr_rw	0.870s	63.369us	20	20	100.00
		rstmgr_csr_aliasing	2.610s	433.332us	5	5	100.00
		rstmgr_same_csr_outstanding	1.640s	284.040us	20	20	100.00
V2	tl_d_partial_access	rstmgr_csr_hw_reset	0.900s	99.780us	5	5	100.00
		rstmgr_csr_rw	0.870s	63.369us	20	20	100.00
		rstmgr_csr_aliasing	2.610s	433.332us	5	5	100.00
		rstmgr_same_csr_outstanding	1.640s	284.040us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	rstmgr_sec_cm	33.100s	16.530ms	5	5	100.00
		rstmgr_tl_intg_err	3.570s	1.105ms	20	20	100.00
V2S	prim_count_check	rstmgr_sec_cm	33.100s	16.530ms	5	5	100.00
V2S	prim_fsm_check	rstmgr_sec_cm	33.100s	16.530ms	5	5	100.00
V2S	sec_cm_bus_integrity	rstmgr_tl_intg_err	3.570s	1.105ms	20	20	100.00
V2S	sec_cm_scan_intersig_mubi	rstmgr_sec_cm_scan_intersig_mubi	1.200s	179.244us	50	50	100.00
V2S	sec_cm_leaf_rst_bkgn_chk	rstmgr_leaf_rst_cnsty	8.500s	2.353ms	49	50	98.00
V2S	sec_cm_leaf_rst_shadow	rstmgr_leaf_rst_shadow_attack	1.180s	243.958us	50	50	100.00
V2S	sec_cm_leaf_fsm_sparse	rstmgr_sec_cm	33.100s	16.530ms	5	5	100.00
V2S	sec_cm_sw_rst_config_regwen	rstmgr_csr_rw	0.870s	63.369us	20	20	100.00
V2S	sec_cm_dump_ctrl_config_regwen	rstmgr_csr_rw	0.870s	63.369us	20	20	100.00
V2S		TOTAL			174	175	99.43
V3	stress_all_with_rand_reset	rstmgr_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			619	620	99.84

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	5	5	4	80.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.44	99.40	99.31	99.87	--	99.83	99.46	98.77

Failure Buckets

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_cnsty_fault did not trigger max_delay:* has 1 failures:
  • Test rstmgr_leaf_rst_cnsty has 1 failures.

    • 11.rstmgr_leaf_rst_cnsty.99385955439886075749498168882425676482246357523206624251152462386324091798145
      Line 263, in log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/11.rstmgr_leaf_rst_cnsty/latest/run.log

        UVM_ERROR @ 130055836 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_cnsty_fault did not trigger max_delay:20
        UVM_INFO @ 130055836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• rstmgr_cnsty_chk
• lint
• 2024.06.11_12.17.44
• 2024.06.10_07.10.33
• 2024.06.08_13.31.33
• 2024.06.07_05.15.20
• 2024.06.06_11.25.16