RSTMGR Simulation Results

Saturday June 29 2024 23:02:35 UTC

GitHub Revision: b33f0bcb4a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 9407974028806500767465982655187958599819354731549473124644158596869486113221

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rstmgr_smoke	1.780s	253.618us	50	50	100.00
V1	csr_hw_reset	rstmgr_csr_hw_reset	0.990s	145.957us	5	5	100.00
V1	csr_rw	rstmgr_csr_rw	0.900s	82.163us	20	20	100.00
V1	csr_bit_bash	rstmgr_csr_bit_bash	10.120s	2.296ms	5	5	100.00
V1	csr_aliasing	rstmgr_csr_aliasing	2.690s	420.625us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rstmgr_csr_mem_rw_with_rand_reset	2.160s	194.449us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rstmgr_csr_rw	0.900s	82.163us	20	20	100.00
		rstmgr_csr_aliasing	2.690s	420.625us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	reset_stretcher	rstmgr_por_stretcher	1.000s	206.459us	50	50	100.00
V2	sw_rst	rstmgr_sw_rst	3.340s	499.207us	50	50	100.00
V2	sw_rst_reset_race	rstmgr_sw_rst_reset_race	1.680s	257.525us	50	50	100.00
V2	reset_info	rstmgr_reset	8.950s	2.039ms	50	50	100.00
V2	cpu_info	rstmgr_reset	8.950s	2.039ms	50	50	100.00
V2	alert_info	rstmgr_reset	8.950s	2.039ms	50	50	100.00
V2	reset_info_capture	rstmgr_reset	8.950s	2.039ms	50	50	100.00
V2	stress_all	rstmgr_stress_all	1.046m	18.185ms	50	50	100.00
V2	alert_test	rstmgr_alert_test	0.990s	165.246us	50	50	100.00
V2	tl_d_oob_addr_access	rstmgr_tl_errors	4.220s	584.582us	20	20	100.00
V2	tl_d_illegal_access	rstmgr_tl_errors	4.220s	584.582us	20	20	100.00
V2	tl_d_outstanding_access	rstmgr_csr_hw_reset	0.990s	145.957us	5	5	100.00
		rstmgr_csr_rw	0.900s	82.163us	20	20	100.00
		rstmgr_csr_aliasing	2.690s	420.625us	5	5	100.00
		rstmgr_same_csr_outstanding	1.540s	224.830us	20	20	100.00
V2	tl_d_partial_access	rstmgr_csr_hw_reset	0.990s	145.957us	5	5	100.00
		rstmgr_csr_rw	0.900s	82.163us	20	20	100.00
		rstmgr_csr_aliasing	2.690s	420.625us	5	5	100.00
		rstmgr_same_csr_outstanding	1.540s	224.830us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	rstmgr_sec_cm	29.790s	16.556ms	5	5	100.00
		rstmgr_tl_intg_err	3.470s	959.501us	20	20	100.00
V2S	prim_count_check	rstmgr_sec_cm	29.790s	16.556ms	5	5	100.00
V2S	prim_fsm_check	rstmgr_sec_cm	29.790s	16.556ms	5	5	100.00
V2S	sec_cm_bus_integrity	rstmgr_tl_intg_err	3.470s	959.501us	20	20	100.00
V2S	sec_cm_scan_intersig_mubi	rstmgr_sec_cm_scan_intersig_mubi	1.400s	182.025us	50	50	100.00
V2S	sec_cm_leaf_rst_bkgn_chk	rstmgr_leaf_rst_cnsty	9.340s	2.180ms	50	50	100.00
V2S	sec_cm_leaf_rst_shadow	rstmgr_leaf_rst_shadow_attack	1.220s	243.573us	50	50	100.00
V2S	sec_cm_leaf_fsm_sparse	rstmgr_sec_cm	29.790s	16.556ms	5	5	100.00
V2S	sec_cm_sw_rst_config_regwen	rstmgr_csr_rw	0.900s	82.163us	20	20	100.00
V2S	sec_cm_dump_ctrl_config_regwen	rstmgr_csr_rw	0.900s	82.163us	20	20	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	rstmgr_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			620	620	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	5	5	5	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.44	99.40	99.31	99.87	--	99.83	99.46	98.77

Past Results

• Latest
• rstmgr_cnsty_chk
• lint
• 2024.06.29_10.01.24
• 2024.06.28_12.18.51
• 2024.06.27_11.35.32
• 2024.06.26_11.33.06
• 2024.06.25_11.56.27