RSTMGR Simulation Results

Friday July 19 2024 23:02:26 UTC

GitHub Revision: e971cd9798

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 26138077499038500271813583950138268511494909685260487774440110801232111361107

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rstmgr_smoke 1.680s 244.706us 50 50 100.00
V1 csr_hw_reset rstmgr_csr_hw_reset 0.960s 150.740us 5 5 100.00
V1 csr_rw rstmgr_csr_rw 0.940s 82.041us 20 20 100.00
V1 csr_bit_bash rstmgr_csr_bit_bash 9.100s 1.536ms 5 5 100.00
V1 csr_aliasing rstmgr_csr_aliasing 1.970s 147.907us 5 5 100.00
V1 csr_mem_rw_with_rand_reset rstmgr_csr_mem_rw_with_rand_reset 1.910s 193.498us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rstmgr_csr_rw 0.940s 82.041us 20 20 100.00
rstmgr_csr_aliasing 1.970s 147.907us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 reset_stretcher rstmgr_por_stretcher 1.090s 228.368us 50 50 100.00
V2 sw_rst rstmgr_sw_rst 3.290s 551.905us 50 50 100.00
V2 sw_rst_reset_race rstmgr_sw_rst_reset_race 1.610s 266.364us 50 50 100.00
V2 reset_info rstmgr_reset 9.420s 2.187ms 50 50 100.00
V2 cpu_info rstmgr_reset 9.420s 2.187ms 50 50 100.00
V2 alert_info rstmgr_reset 9.420s 2.187ms 50 50 100.00
V2 reset_info_capture rstmgr_reset 9.420s 2.187ms 50 50 100.00
V2 stress_all rstmgr_stress_all 1.097m 19.441ms 50 50 100.00
V2 alert_test rstmgr_alert_test 0.950s 135.781us 50 50 100.00
V2 tl_d_oob_addr_access rstmgr_tl_errors 3.570s 566.193us 20 20 100.00
V2 tl_d_illegal_access rstmgr_tl_errors 3.570s 566.193us 20 20 100.00
V2 tl_d_outstanding_access rstmgr_csr_hw_reset 0.960s 150.740us 5 5 100.00
rstmgr_csr_rw 0.940s 82.041us 20 20 100.00
rstmgr_csr_aliasing 1.970s 147.907us 5 5 100.00
rstmgr_same_csr_outstanding 1.690s 225.238us 20 20 100.00
V2 tl_d_partial_access rstmgr_csr_hw_reset 0.960s 150.740us 5 5 100.00
rstmgr_csr_rw 0.940s 82.041us 20 20 100.00
rstmgr_csr_aliasing 1.970s 147.907us 5 5 100.00
rstmgr_same_csr_outstanding 1.690s 225.238us 20 20 100.00
V2 TOTAL 340 340 100.00
V2S tl_intg_err rstmgr_sec_cm 29.930s 16.561ms 5 5 100.00
rstmgr_tl_intg_err 3.430s 875.488us 20 20 100.00
V2S prim_count_check rstmgr_sec_cm 29.930s 16.561ms 5 5 100.00
V2S prim_fsm_check rstmgr_sec_cm 29.930s 16.561ms 5 5 100.00
V2S sec_cm_bus_integrity rstmgr_tl_intg_err 3.430s 875.488us 20 20 100.00
V2S sec_cm_scan_intersig_mubi rstmgr_sec_cm_scan_intersig_mubi 1.330s 175.487us 50 50 100.00
V2S sec_cm_leaf_rst_bkgn_chk rstmgr_leaf_rst_cnsty 10.000s 2.368ms 49 50 98.00
V2S sec_cm_leaf_rst_shadow rstmgr_leaf_rst_shadow_attack 1.190s 244.070us 50 50 100.00
V2S sec_cm_leaf_fsm_sparse rstmgr_sec_cm 29.930s 16.561ms 5 5 100.00
V2S sec_cm_sw_rst_config_regwen rstmgr_csr_rw 0.940s 82.041us 20 20 100.00
V2S sec_cm_dump_ctrl_config_regwen rstmgr_csr_rw 0.940s 82.041us 20 20 100.00
V2S TOTAL 174 175 99.43
V3 stress_all_with_rand_reset rstmgr_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 619 620 99.84

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 8 8 8 100.00
V2S 5 5 4 80.00
V3 1 0 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.40 99.40 99.31 99.87 -- 99.83 99.46 98.52

Failure Buckets

Past Results