RSTMGR Simulation Results

Saturday August 10 2024 23:02:23 UTC

GitHub Revision: 07b417ef03

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2196818177928134427831197337249851347498377272679561983541244979366753055772

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rstmgr_smoke 1.640s 245.651us 50 50 100.00
V1 csr_hw_reset rstmgr_csr_hw_reset 0.920s 140.658us 5 5 100.00
V1 csr_rw rstmgr_csr_rw 0.910s 88.068us 20 20 100.00
V1 csr_bit_bash rstmgr_csr_bit_bash 9.740s 2.278ms 5 5 100.00
V1 csr_aliasing rstmgr_csr_aliasing 2.640s 445.655us 5 5 100.00
V1 csr_mem_rw_with_rand_reset rstmgr_csr_mem_rw_with_rand_reset 1.790s 189.232us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rstmgr_csr_rw 0.910s 88.068us 20 20 100.00
rstmgr_csr_aliasing 2.640s 445.655us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 reset_stretcher rstmgr_por_stretcher 1.120s 261.949us 50 50 100.00
V2 sw_rst rstmgr_sw_rst 3.140s 541.069us 50 50 100.00
V2 sw_rst_reset_race rstmgr_sw_rst_reset_race 1.570s 269.238us 50 50 100.00
V2 reset_info rstmgr_reset 8.780s 2.150ms 50 50 100.00
V2 cpu_info rstmgr_reset 8.780s 2.150ms 50 50 100.00
V2 alert_info rstmgr_reset 8.780s 2.150ms 50 50 100.00
V2 reset_info_capture rstmgr_reset 8.780s 2.150ms 50 50 100.00
V2 stress_all rstmgr_stress_all 49.260s 13.658ms 50 50 100.00
V2 alert_test rstmgr_alert_test 0.910s 99.873us 50 50 100.00
V2 tl_d_oob_addr_access rstmgr_tl_errors 3.970s 645.325us 20 20 100.00
V2 tl_d_illegal_access rstmgr_tl_errors 3.970s 645.325us 20 20 100.00
V2 tl_d_outstanding_access rstmgr_csr_hw_reset 0.920s 140.658us 5 5 100.00
rstmgr_csr_rw 0.910s 88.068us 20 20 100.00
rstmgr_csr_aliasing 2.640s 445.655us 5 5 100.00
rstmgr_same_csr_outstanding 1.690s 266.402us 20 20 100.00
V2 tl_d_partial_access rstmgr_csr_hw_reset 0.920s 140.658us 5 5 100.00
rstmgr_csr_rw 0.910s 88.068us 20 20 100.00
rstmgr_csr_aliasing 2.640s 445.655us 5 5 100.00
rstmgr_same_csr_outstanding 1.690s 266.402us 20 20 100.00
V2 TOTAL 340 340 100.00
V2S tl_intg_err rstmgr_sec_cm 25.980s 16.616ms 5 5 100.00
rstmgr_tl_intg_err 3.280s 946.087us 20 20 100.00
V2S prim_count_check rstmgr_sec_cm 25.980s 16.616ms 5 5 100.00
V2S prim_fsm_check rstmgr_sec_cm 25.980s 16.616ms 5 5 100.00
V2S sec_cm_bus_integrity rstmgr_tl_intg_err 3.280s 946.087us 20 20 100.00
V2S sec_cm_scan_intersig_mubi rstmgr_sec_cm_scan_intersig_mubi 1.310s 174.239us 50 50 100.00
V2S sec_cm_leaf_rst_bkgn_chk rstmgr_leaf_rst_cnsty 9.000s 2.359ms 49 50 98.00
V2S sec_cm_leaf_rst_shadow rstmgr_leaf_rst_shadow_attack 1.200s 244.788us 50 50 100.00
V2S sec_cm_leaf_fsm_sparse rstmgr_sec_cm 25.980s 16.616ms 5 5 100.00
V2S sec_cm_sw_rst_config_regwen rstmgr_csr_rw 0.910s 88.068us 20 20 100.00
V2S sec_cm_dump_ctrl_config_regwen rstmgr_csr_rw 0.910s 88.068us 20 20 100.00
V2S TOTAL 174 175 99.43
V3 stress_all_with_rand_reset rstmgr_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 619 620 99.84

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 8 8 8 100.00
V2S 5 5 4 80.00
V3 1 0 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.44 99.40 99.31 99.87 -- 99.83 99.46 98.77

Failure Buckets

Past Results