RSTMGR Simulation Results

Thursday August 22 2024 22:02:20 UTC

GitHub Revision: 0825c81be0

Branch: os_regression_2024_08_22

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 102736032995262985039236458937944411119924968439319752111682827040046827694889

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rstmgr_smoke 1.540s 261.334us 50 50 100.00
V1 csr_hw_reset rstmgr_csr_hw_reset 0.840s 118.405us 5 5 100.00
V1 csr_rw rstmgr_csr_rw 0.780s 65.526us 20 20 100.00
V1 csr_bit_bash rstmgr_csr_bit_bash 7.360s 1.551ms 5 5 100.00
V1 csr_aliasing rstmgr_csr_aliasing 1.720s 162.707us 5 5 100.00
V1 csr_mem_rw_with_rand_reset rstmgr_csr_mem_rw_with_rand_reset 1.450s 167.198us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rstmgr_csr_rw 0.780s 65.526us 20 20 100.00
rstmgr_csr_aliasing 1.720s 162.707us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 reset_stretcher rstmgr_por_stretcher 0.910s 220.694us 50 50 100.00
V2 sw_rst rstmgr_sw_rst 2.210s 451.290us 50 50 100.00
V2 sw_rst_reset_race rstmgr_sw_rst_reset_race 1.290s 276.359us 50 50 100.00
V2 reset_info rstmgr_reset 6.710s 1.830ms 50 50 100.00
V2 cpu_info rstmgr_reset 6.710s 1.830ms 50 50 100.00
V2 alert_info rstmgr_reset 6.710s 1.830ms 50 50 100.00
V2 reset_info_capture rstmgr_reset 6.710s 1.830ms 50 50 100.00
V2 stress_all rstmgr_stress_all 48.050s 14.656ms 50 50 100.00
V2 alert_test rstmgr_alert_test 0.880s 172.500us 50 50 100.00
V2 tl_d_oob_addr_access rstmgr_tl_errors 3.080s 482.666us 20 20 100.00
V2 tl_d_illegal_access rstmgr_tl_errors 3.080s 482.666us 20 20 100.00
V2 tl_d_outstanding_access rstmgr_csr_hw_reset 0.840s 118.405us 5 5 100.00
rstmgr_csr_rw 0.780s 65.526us 20 20 100.00
rstmgr_csr_aliasing 1.720s 162.707us 5 5 100.00
rstmgr_same_csr_outstanding 1.580s 245.619us 20 20 100.00
V2 tl_d_partial_access rstmgr_csr_hw_reset 0.840s 118.405us 5 5 100.00
rstmgr_csr_rw 0.780s 65.526us 20 20 100.00
rstmgr_csr_aliasing 1.720s 162.707us 5 5 100.00
rstmgr_same_csr_outstanding 1.580s 245.619us 20 20 100.00
V2 TOTAL 340 340 100.00
V2S tl_intg_err rstmgr_sec_cm 28.930s 16.514ms 5 5 100.00
rstmgr_tl_intg_err 3.140s 930.947us 20 20 100.00
V2S prim_count_check rstmgr_sec_cm 28.930s 16.514ms 5 5 100.00
V2S prim_fsm_check rstmgr_sec_cm 28.930s 16.514ms 5 5 100.00
V2S sec_cm_bus_integrity rstmgr_tl_intg_err 3.140s 930.947us 20 20 100.00
V2S sec_cm_scan_intersig_mubi rstmgr_sec_cm_scan_intersig_mubi 1.140s 168.747us 50 50 100.00
V2S sec_cm_leaf_rst_bkgn_chk rstmgr_leaf_rst_cnsty 8.350s 2.237ms 50 50 100.00
V2S sec_cm_leaf_rst_shadow rstmgr_leaf_rst_shadow_attack 1.140s 301.868us 50 50 100.00
V2S sec_cm_leaf_fsm_sparse rstmgr_sec_cm 28.930s 16.514ms 5 5 100.00
V2S sec_cm_sw_rst_config_regwen rstmgr_csr_rw 0.780s 65.526us 20 20 100.00
V2S sec_cm_dump_ctrl_config_regwen rstmgr_csr_rw 0.780s 65.526us 20 20 100.00
V2S TOTAL 175 175 100.00
V3 stress_all_with_rand_reset rstmgr_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 620 620 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 8 8 8 100.00
V2S 5 5 5 100.00
V3 1 0 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.46 99.40 99.31 100.00 -- 99.83 99.46 98.77

Past Results