Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	570947	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

344985

1

T2

61

T3

6

T4

59

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	486937	1			T1	1		T2	81		T4	99
values[0x0]	213979	1			T2	47		T3	11		T4	51
values[0x1]	215016	1			T2	38		T3	8		T4	62

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	479285	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

436647

1

T2

67

T3

8

T4

87

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4410	1			T8	2		T10	3		T11	28
valid_sources[0x01]	3704	1			T4	1		T8	4		T11	8
valid_sources[0x02]	2549	1			T4	1		T10	6		T11	6
valid_sources[0x03]	6409	1			T4	2		T8	1		T10	3
valid_sources[0x04]	3409	1			T2	1		T8	2		T10	9
valid_sources[0x05]	3385	1			T2	7		T8	2		T10	2
valid_sources[0x06]	2843	1			T6	3		T8	3		T10	4
valid_sources[0x07]	3065	1			T2	4		T6	2		T8	2
valid_sources[0x08]	3273	1			T4	1		T8	2		T10	5
valid_sources[0x09]	3091	1			T2	1		T4	2		T8	1
valid_sources[0x0a]	3962	1			T10	3		T11	16		T12	30
valid_sources[0x0b]	2805	1			T8	2		T10	4		T11	10
valid_sources[0x0c]	3459	1			T4	1		T6	3		T8	1
valid_sources[0x0d]	5337	1			T6	1		T8	1		T12	11
valid_sources[0x0e]	2802	1			T8	1		T10	28		T12	12
valid_sources[0x0f]	3253	1			T8	1		T10	1		T11	17
valid_sources[0x10]	3618	1			T2	2		T10	1		T11	8
valid_sources[0x11]	4251	1			T2	2		T4	1		T8	3
valid_sources[0x12]	3204	1			T6	5		T10	4		T11	12
valid_sources[0x13]	3425	1			T8	1		T10	12		T11	2
valid_sources[0x14]	8060	1			T4	1		T8	2		T10	8
valid_sources[0x15]	4039	1			T4	2		T8	3		T11	15
valid_sources[0x16]	4022	1			T6	3		T10	4		T11	4
valid_sources[0x17]	3315	1			T2	4		T6	6		T8	2
valid_sources[0x18]	3870	1			T4	1		T10	8		T11	8
valid_sources[0x19]	3896	1			T8	2		T11	16		T12	15
valid_sources[0x1a]	3540	1			T10	5		T11	8		T12	6
valid_sources[0x1b]	2572	1			T3	1		T6	1		T10	3
valid_sources[0x1c]	2646	1			T2	4		T4	1		T6	11
valid_sources[0x1d]	3959	1			T2	2		T4	1		T8	2
valid_sources[0x1e]	3049	1			T4	2		T8	1		T10	6
valid_sources[0x1f]	2714	1			T6	6		T10	17		T12	17
valid_sources[0x20]	2800	1			T4	3		T8	2		T10	1
valid_sources[0x21]	5176	1			T8	4		T10	3		T11	16
valid_sources[0x22]	2999	1			T4	1		T8	1		T10	2
valid_sources[0x23]	3180	1			T2	4		T4	1		T6	1
valid_sources[0x24]	3164	1			T6	4		T10	1		T11	39
valid_sources[0x25]	3297	1			T8	3		T11	26		T12	18
valid_sources[0x26]	3679	1			T8	2		T10	5		T11	3
valid_sources[0x27]	3361	1			T6	2		T10	1		T11	33
valid_sources[0x28]	5401	1			T2	2		T4	2		T8	2
valid_sources[0x29]	3748	1			T4	3		T10	1		T11	1
valid_sources[0x2a]	2775	1			T2	3		T6	2		T10	10
valid_sources[0x2b]	4129	1			T8	4		T10	1		T12	13
valid_sources[0x2c]	3292	1			T6	9		T8	1		T10	7
valid_sources[0x2d]	3250	1			T2	4		T4	1		T6	1
valid_sources[0x2e]	2554	1			T4	2		T8	1		T11	6
valid_sources[0x2f]	2940	1			T4	3		T8	2		T12	31
valid_sources[0x30]	2748	1			T2	2		T4	3		T8	3
valid_sources[0x31]	2558	1			T4	1		T8	1		T11	3
valid_sources[0x32]	3177	1			T2	1		T8	2		T10	12
valid_sources[0x33]	3418	1			T2	3		T4	1		T8	2
valid_sources[0x34]	3388	1			T3	1		T4	1		T10	4
valid_sources[0x35]	3067	1			T4	2		T11	10		T12	15
valid_sources[0x36]	3885	1			T2	2		T10	3		T11	1
valid_sources[0x37]	3398	1			T8	3		T10	9		T11	9
valid_sources[0x38]	6644	1			T10	4		T11	21		T12	21
valid_sources[0x39]	3096	1			T8	3		T10	25		T11	11
valid_sources[0x3a]	3512	1			T2	1		T4	2		T6	7
valid_sources[0x3b]	3048	1			T2	2		T4	2		T6	3
valid_sources[0x3c]	3798	1			T3	1		T6	2		T8	4
valid_sources[0x3d]	2811	1			T2	1		T8	1		T10	9
valid_sources[0x3e]	3045	1			T2	1		T8	7		T11	3
valid_sources[0x3f]	3607	1			T8	2		T10	7		T12	14
valid_sources[0x40]	4009	1			T4	1		T6	3		T8	2
valid_sources[0x41]	2671	1			T2	2		T10	4		T11	24
valid_sources[0x42]	2822	1			T2	1		T6	2		T11	8
valid_sources[0x43]	3142	1			T10	8		T11	1		T12	13
valid_sources[0x44]	3333	1			T2	3		T4	1		T12	18
valid_sources[0x45]	2929	1			T3	1		T4	1		T6	5
valid_sources[0x46]	3769	1			T3	2		T4	3		T10	1
valid_sources[0x47]	2767	1			T12	13		T13	22		T14	8
valid_sources[0x48]	3721	1			T4	2		T8	2		T10	3
valid_sources[0x49]	3238	1			T8	4		T10	4		T11	36
valid_sources[0x4a]	2662	1			T8	1		T10	3		T12	4
valid_sources[0x4b]	2740	1			T8	1		T10	1		T12	14
valid_sources[0x4c]	2404	1			T4	1		T6	1		T8	2
valid_sources[0x4d]	3000	1			T2	3		T6	2		T8	2
valid_sources[0x4e]	3098	1			T8	1		T10	6		T11	27
valid_sources[0x4f]	4234	1			T8	1		T10	5		T11	9
valid_sources[0x50]	2816	1			T8	1		T10	8		T11	11
valid_sources[0x51]	6911	1			T2	5		T4	2		T8	4
valid_sources[0x52]	3174	1			T2	3		T4	1		T10	1
valid_sources[0x53]	4263	1			T6	2		T8	1		T10	4
valid_sources[0x54]	2579	1			T3	2		T4	2		T6	5
valid_sources[0x55]	3100	1			T2	1		T4	3		T8	2
valid_sources[0x56]	4155	1			T2	1		T4	1		T11	1
valid_sources[0x57]	4344	1			T6	8		T8	1		T10	11
valid_sources[0x58]	3251	1			T8	3		T10	1		T11	31
valid_sources[0x59]	3863	1			T4	2		T6	1		T8	3
valid_sources[0x5a]	6645	1			T6	5		T10	5		T11	6
valid_sources[0x5b]	3110	1			T10	8		T11	6		T12	19
valid_sources[0x5c]	3148	1			T10	5		T11	2		T12	23
valid_sources[0x5d]	3839	1			T4	1		T6	10		T10	5
valid_sources[0x5e]	4412	1			T4	1		T8	8		T11	24
valid_sources[0x5f]	3413	1			T8	2		T12	18		T13	21
valid_sources[0x60]	3580	1			T2	2		T4	2		T8	1
valid_sources[0x61]	3509	1			T10	8		T11	7		T12	8
valid_sources[0x62]	3767	1			T6	1		T8	1		T10	2
valid_sources[0x63]	4394	1			T4	2		T6	1		T8	3
valid_sources[0x64]	3737	1			T6	6		T8	2		T11	12
valid_sources[0x65]	3188	1			T4	1		T6	14		T11	26
valid_sources[0x66]	3219	1			T2	2		T10	9		T11	3
valid_sources[0x67]	3166	1			T2	1		T8	4		T10	11
valid_sources[0x68]	2906	1			T2	2		T8	1		T11	10
valid_sources[0x69]	3943	1			T2	1		T8	1		T10	20
valid_sources[0x6a]	3263	1			T2	7		T10	5		T11	12
valid_sources[0x6b]	3371	1			T4	1		T8	4		T11	1
valid_sources[0x6c]	3000	1			T8	1		T10	6		T11	11
valid_sources[0x6d]	3247	1			T2	2		T8	6		T10	1
valid_sources[0x6e]	2861	1			T4	2		T6	1		T8	3
valid_sources[0x6f]	6522	1			T2	2		T4	2		T8	2
valid_sources[0x70]	4223	1			T11	1		T12	14		T13	7
valid_sources[0x71]	6221	1			T4	3		T8	3		T11	7
valid_sources[0x72]	6740	1			T4	1		T8	2		T12	11
valid_sources[0x73]	3198	1			T8	2		T10	7		T11	11
valid_sources[0x74]	2674	1			T3	1		T6	8		T8	1
valid_sources[0x75]	3015	1			T8	2		T10	5		T11	7
valid_sources[0x76]	4065	1			T4	1		T10	6		T11	2
valid_sources[0x77]	5673	1			T2	4		T6	9		T8	3
valid_sources[0x78]	2878	1			T4	4		T6	8		T8	1
valid_sources[0x79]	3525	1			T4	1		T6	7		T8	1
valid_sources[0x7a]	3257	1			T4	2		T10	9		T11	5
valid_sources[0x7b]	3503	1			T8	2		T10	17		T11	5
valid_sources[0x7c]	3948	1			T2	1		T4	1		T10	3
valid_sources[0x7d]	2904	1			T4	3		T6	12		T8	2
valid_sources[0x7e]	3677	1			T2	2		T8	1		T10	16
valid_sources[0x7f]	3738	1			T6	5		T10	12		T11	32
valid_sources[0x80]	3687	1			T4	1		T8	1		T10	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

229201

1

T2

40

T4

39

T6

76

values[0x0]

all_enables

biggest_size

75127

1

T2

17

T3

5

T4

9

values[0x1]

all_enables

biggest_size

40657

1

T2

4

T3

1

T4

11